38. DAC 2001:
Las Vegas, Nevada, USA Panel
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Nanometer Futures
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Wojciech Maly :
IC Design in High-Cost Nanometer-Technologies Era.
9-14
System-Level Configurability:
Bus, Interface, and Processor Design
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conf/dac/MeguerdichianDK01 export record as
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Making Verification More Efficient
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SoC and High-Level DFT
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Bulent I. Dervisoglu :
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers.
53-58
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Panel
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Design for Subwavelength Manufacturability:
Impact on EDA
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conf/dac/SchellenbergTCS01 export record as
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New Ideas in Logic Synthesis
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Analog Design and Modeling
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Jafar Savoj ,
Behzad Razavi :
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems.
121-126
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Scan-Based Testing
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Irith Pomeranz :
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits.
145-150
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Panel
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conf/dac/MorettiHNCKABDF01
Configurable Computing:
Reconfiguring the Industry
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Interconnect Design Optimization
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Power Estimation Techniques
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Functional Validation Based on Boolean Reasoning (BDD, SAT)
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Verification:
Life Beyond Algorithms
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Bob Bentley :
Validating the Intel Pentium 4 Microprocessor.
244-248
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Ken Albin :
Nuts and Bolts of Core and SoC Verification.
249-252
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Dissecting an Embedded System:
Lessons from Bluetooth
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Algorithmic and Compiler Transformations for High-Level Synthesis
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Kiran Bondalapati :
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching.
273-276
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Gate Delay Calculation
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Memory, Bus and Current Testing
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Kaamran Raahemifar ,
Majid Ahmadi :
Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits.
313-316
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Panel
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conf/dac/RutenbarBDJORS01
Inductance 101 and Beyond
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Memory Optimization Techniques for DSP Processors
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conf/dac/UdayanarayananC01 export record as
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Technology Dependant Logic Synthesis
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Jason Cong ,
Michail Romesis :
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping.
389-394
Collaborative and Distributed Design Frameworks
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Panel
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conf/dac/GielenSMKHKMMRY01
Closing the Gap Between ASIC and Custom:
Design Examples
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Energy and Flexibility Driven Scheduling
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Jiong Luo ,
Niraj K. Jha :
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems.
444-449
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Representation and Optimization for Digital Arithmetic Circuits
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Anmol Mathur ,
Sanjeev Saluja :
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis.
462-467
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Techniques for IP Protection
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Gang Qu :
Publicly Detectable Techniques for the Protection of Virtual Components.
474-479
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Visualization and Animation for VLSI Design
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Application-Specific Customization for Systems-on-a-Chip
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Peter Petrov ,
Alex Orailoglu :
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
512-517
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Satisfiability Solvers and Techniques
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Power and Interconnect Analysis
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Domain Specific Design Methodologies
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conf/dac/MeguerdichianKMPP01
Panel
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Analysis and Implementation for Embedded Systems
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Industrial Case Studies in Verification
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Integrated High-Level Synthesis Based Solutions
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Alex Doboli ,
Ranga Vemuri :
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints.
629-634
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Timing Verification and Simulation
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On-Chip Communication Architectures
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Drew Wingard :
MicroNetwork-Based Integration for SOCs.
673-677
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Compiler and Architecture Interactions
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Timing with Crosstalk
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Low Power Design:
Systems to Interconnect
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Floorplanning Representations and Placement Algorithms
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Panel
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Signal Integrity:
Avoidance and Test Techniques
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Kaustav Banerjee ,
Amit Mehrotra :
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects.
798-803
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Novel Approaches to Microprocessor Design and Verification
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Scheduling Techniques for Power Management
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Gang Quan ,
Xiaobo Hu :
Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors.
828-833
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Novel Devices and Yield Optimization
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