CODES 1998: Seattle, Washington, USA

• Pai H. Chou, Gaetano Borriello:
  An analysis-based approach to composition of distributed embedded systems. 3-7
  
• Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele:
  Combining multiple models of computation for scheduling and allocation. 9-13
  
• Claudio Passerone, Roberto Passerone, Claudio Sansoè, Jonathan Martin, Alberto L. Sangiovanni-Vincentelli, Rick McGeer:
  Modeling reactive systems in Java. 15-19
  
• Jörg Henkel, Yanbing Li:
  Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. 23-27
  
• Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
  HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. 29-33
  
• Franz Fischer, Annette Muth, Georg Färber:
  Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment. 35-39
  
• Michael Eisenring, Jürgen Teich:
  Domain-specific interface generation from dataflow specifications. 43-47
  
• Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet:
  Communication synthesis and HW/SW integration for embedded system design. 49-53
  
• Peter Voigt Knudsen, Jan Madsen:
  Communication estimation for hardware/software codesign. 55-59
  
• Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli:
  Software timing analysis using HW/SW cosimulation and instruction set simulator. 65-69
  
• Sungjoo Yoo, Kiyoung Choi:
  Optimistic distributed timed cosimulation based on thread simulation model. 71-75
  
• Giuseppe Del Castillo, Wolfram Hardt:
  Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models. 77-81
  
• Luc Bianco, Michel Auguin, Guy Gogniat, Alain Pegatoquet:
  A path analysis based partitioning for time constrained embedded systems. 85-89
  
• Frank Slomka, Jürgen Zant, Lennard Lambert:
  Schedulability analysis of heterogeneous systems for performance message sequence chart. 91-95
  
• Robert P. Dick, David L. Rhodes, Wayne Wolf:
  TGFF: task graphs for free. 97-101
  
• Josef Fleischmann, Klaus Buchenrieder, Rainer Kress:
  A hardware/software prototyping environment for dynamically reconfigurable embedded systems. 105-109
  
• Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya:
  Hardware/software co-design of an ATM network interface card: a case study. 111-115
  
• Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
  A case study on modeling shared memory access effects during performance analysis of HW/SW systems. 117-121
  
• Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf:
  The construction of a retargetable simulator for an architecture template. 125-129
  
• Jian Li, Rajesh K. Gupta:
  HDL code restructuring using timed decision tables. 131-135
  
• Karam S. Chatha, Ranga Vemuri:
  RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. 139-143
  
• Peter Grun, Florin Balasa, Nikil D. Dutt:
  Memory size estimation for multimedia applications. 145-149
  

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