CICC 2010: San Jose, California, USA

Advanced Embedded Memories

• Mark Jacunski, Darren Anand, Robert Busch, John Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale Pontius, Michael Roberge, Stephen Sliva:
  A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. 1-4
  
• Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun:
  Improving SRAM Vmin and yield by using variation-aware BTI stress. 1-4
  
• Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim:
  Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. 1-4
  
• Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  7T SRAM enabling low-energy simultaneous block copy. 1-4
  
• Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka:
  A 32nm 0.5V-supply dual-read 6T SRAM. 1-4
  

Technology Variability Modeling

• Asen Asenov, Binjie Cheng, Daryoosh Dideban, Urban Kovac, Negin Moezi, Campbell Millar, Gareth Roy, Andrew R. Brown, Scott Roy:
  Modeling and simulation of transistor and circuit variability and reliability. 1-8
  
• Borivoje Nikolic, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Ji-Hoon Park, Seng Oon Toh:
  Technology variability from a design perspective. 1-8
  
• Gokce Keskin, Jonathan Proesel, Larry T. Pileggi:
  Statistical modeling and post manufacturing configuration for scaled analog CMOS. 1-4
  

Advanced and Specialty IC Technologies

• Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka:
  Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. 1-4
  
• Vivek Joshi, Michael Wieckowski, Gregory K. Chen, David Blaauw, Dennis Sylvester:
  Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS. 1-4
  
• Lynn T.-N. Wang, Nuo Xu, Seng Oon Toh, Andrew R. Neureuther, Tsu-Jae King Liu, Borivoje Nikolic:
  Parameter-specific ring oscillator for process monitoring at the 45 nm node. 1-4
  
• Samir Chaudhry, Marco Racanelli:
  Specialty Foundry technology and design enablement for RF, high performance analog, and power. 1-4
  

RF Transceivers

• Hooman Darabi:
  Highly integrated and tunable RF front-ends for reconfigurable multi-band transceivers. 1-8
  
• Paul Yu, Todd Sepke, Belal Helal, Shervin Shekarchian, Danilo Gerna, Konstantinos Sarrigeorgidis, Lydi Smaini, Arnab Mitra, James Li, Brian Brunn, Greg Uehara, Thomas Cho:
  A 1.2 mm² fully integrated GPS radio with cellular/WiFi Co-existence. 1-4
  
• David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn:
  A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC. 1-4
  
• Zhiwei Xu, Qun Jane Gu, Yi-Cheng Wu, Adrian Tang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang:
  D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link. 1-4
  

Analog Technologies

• Yannis P. Tsividis:
  Event-driven data acquisition and continuous-time digital signal processing. 1-8
  
• Jingxue Lu, Ranjit Gharpurey:
  A self oscillating class D audio amplifier with 0.0012% THD+N and 116.5 dB dynamic range. 1-4
  
• Seungchul Jung, Young-Jin Woo, Tae-Kyu Nam, Jinyong Jeon, Gyu-Ha Cho, Gyu-Hyeong Cho:
  Dynamic push-pull operational amplifier for AMLCD common voltage driver using minimum current limiting circuit. 1-4
  
• Peiyuan Wan, Yun Chiu, Pingfen Lin:
  A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3. 1-4
  
• Hassan O. Elwan, Ahmet Tekin, Kenneth Pedrotti:
  A low-noise analog baseband in 65nm CMOS. 1-4
  
• Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu:
  A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. 1-4
  
• Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu:
  A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. 1-4
  
• Xiaoyan Gui, Michael M. Green:
  High-speed CMOS ring oscillators with low supply sensitivity. 1-4
  

Biomedical Sensors and Systems

• Marco Tartagni:
  Smart CMOS substrates for bioelectronic interfaces: Overview and trends. 1-8
  
• Fan Zhang, Apurva Mishra, Andrew G. Richardson, Stavros Zanos, Brian P. Otis:
  A low-power multi-band ECoG/EEG interface IC. 1-4
  
• Henrique Miranda, Teresa H. Meng:
  A programmable pulse UWB transmitter with 34% energy efficiency for multichannel neuro-recording systems. 1-4
  
• Edward K. F. Lee:
  An inside body power and bidirectional data transfer IC module pair. 1-4
  
• Meisam Honarvar Nazari, Hamed Mazhab-Jafari, Lian Leng, Axel Guenther, Roman Genov:
  192-channel CMOS neurochemical microarray. 1-4
  
• Hua Wang, Constantine Sideris, Ali Hajimiri:
  A frequency-shift based CMOS magnetic biosensor with spatially uniform sensor transducer gain. 1-4
  

Advanced Wireline Techniques

• Dustin Dunwell, Anthony Chan Carusone:
  Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. 1-4
  
• Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe:
  Equalizer design and performance trade-offs in ADC-based serial links. 1-8
  
• Tina Tahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Masaya Kibune:
  A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. 1-4
  
• Taehyoun Oh, Ramesh Harjani:
  A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. 1-4
  
• Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda:
  A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. 1-4
  
• Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
  A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. 1-4
  
• Ranko Sredojevic, Vladimir Stojanovic:
  Digital link pre-emphasis with dynamic driver impedance modulation. 1-4
  

Oversampled Data Converters

• Sherif Galal, Jurgen van Engelen, Jared Welz, Henrik Jensen, Khaled Abdelfattah, Felix Cheung, Sasi Kumar Arunachalam, Xicheng Jiang, Todd Brooks:
  A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique. 1-4
  
• Wenhuan Yu, Mehmet Aslan, Gabor C. Temes:
  82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction. 1-4
  
• Nima Maghari, Skyler Weaver, Un-Ku Moon:
  A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator. 1-4
  
• Jeongseok Chae, Sanghyeon Lee, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes:
  A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. 1-4
  
• Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho:
  A 69.8 dB SNDR 3^rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver. 1-4
  
• Mohammad Ranjbar, Omid Oliaei, Robert W. Jackson:
  A robust STF 6mW CT ΔΣ modulator with 76dB dynamic range and 5MHz bandwidth. 1-4
  
• Bart De Vuyst, Pieter Rombouts:
  5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025mm². 1-4
  

Power Management

• Edward N. Y. Ho, Philip K. T. Mok:
  Ramp signal generation in Voltage mode CCM Random switching Frequency Buck converter for conductive EMI reduction. 1-4
  
• Mengmeng Du, Hoi Lee:
  A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current control. 1-4
  
• Sudhir S. Kudva, Ramesh Harjani:
  Fully integrated on-chip DC-DC converter with a 450x output range. 1-4
  
• Ahmed Amer, Edgar Sánchez-Sinencio:
  A 140mA 90nm CMOS low drop-out regulator with -56dB power supply rejection at 10MHz. 1-4
  
• Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai:
  0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. 1-4
  
• Yujia Yang, Fabio Bisogno, Sadachai Nittayarumphong, Matthias Radecker, Marc Fahlenkamp, Wolf-Joachim Fischer:
  Smart universal control IC for high loaded factor resonant converters. 1-4
  

Low Phase Noise VCOS and ADPLL Building Blocks

• Zhiming Deng, Ali M. Niknejad:
  A 4-port-inductor-based VCO coupling method for phase noise reduction. 1-4
  
• Diptendu Ghosh, Stewart S. Taylor, Yulin Tan, Ranjit Gharpurey:
  A 10 GHz low phase noise VCO employing current reuse and capacitive power combining. 1-4
  
• Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez:
  A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. 1-4
  
• Chengjie Zuo, Jan Van der Spiegel, Gianluca Piazza:
  1.5-GHz CMOS voltage-controlled oscillator based on thickness-field-excited piezoelectric AlN contour-mode MEMS resonators. 1-4
  
• Julie R. Hu, Richard C. Ruby, Brian P. Otis:
  A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS. 1-4
  
• Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski, Fikret Dulger, Socrates D. Vamvakos:
  Spurious free time-to-digital conversion in an ADPLL using short dithering sequences. 1-4
  
• Jianjun Yu, Fa Foster Dai:
  A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS. 1-4
  

Novel Simulation and Modeling Techniques

• G. Peter Fang, Rod Burt, Ning Dong:
  Loop finder analysis for analog circuits. 1-4
  
• Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs:
  Noise analysis of non-linear dynamic integrated circuits. 1-4
  
• Takaaki Okumura, Masanori Hashimoto:
  Setup time, hold time and clock-to-Q delay computation under dynamic supply noise. 1-4
  
• Paul T. M. van Zeijl, Henry T. van der Zanden, Bob B. A. Theunissen, Henk A. H. Termeer:
  Modelling and Measurements on minimum-width transmission-lines from 10-67GHz in 65nm CMOS. 1-4
  
• Dajie Zeng, Hongrui Wang, Dongxu Yang, Li Zhang, Yan Wang, Zhiping Yu, Yaohui Zhang:
  A novel equivalent circuit for on chip transmission lines modeling. 1-4
  

3D Design Considerations

• Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
  Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. 1-4
  
• Mark Nakamoto, Riko Radojcic, Wei Zhao, Vinay K. Dasarapu, Aditya P. Karmarkar, Xiaopeng Xu:
  Simulation methodology and flow integration for 3D IC stress management. 1-4
  
• Yoonmyung Lee, Gregory K. Chen, Scott Hanson, Dennis Sylvester, David Blaauw:
  Ultra-low power circuit techniques for a new class of sub-mm³ sensor nodes. 1-8
  

Optical Communication IC's and PLL's

• Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura:
  A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. 1-4
  
• Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao:
  Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors. 1-8
  
• Joohwa Kim, James F. Buckwalter:
  A 40-Gb/s optical transceiver front-end in 45nm SOI CMOS technology. 1-4
  
• Norio Chujo, Tsuneo Kawamata, Kenichi Ohhata, Toshinobu Ohno:
  A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects. 1-4
  
• Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
  A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. 1-4
  
• John Crossley, Eric Naviasky, Elad Alon:
  An energy-efficient ring-oscillator digital PLL. 1-4
  
• Chin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee:
  An offset phase-locked loop spread spectrum clock generator for SATA III. 1-4
  

On Die Test and Debug Enabler at 65nm and Beyond

• Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De:
  Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. 1-4
  
• Prashant Singh, Eric Karl, Dennis Sylvester, David Blaauw:
  Dynamic NBTI management using a 45nm multi-degradation sensor. 1-4
  
• Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
  EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision. 1-4
  

Nyquist ADCs

• Jonathan Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi:
  An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. 1-4
  
• Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Patrick Yin Chiang:
  Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS. 1-4
  
• Sang-Hyun Cho, Chang-Kyo Lee, Jong-Kee Kwon, Seung-Tak Ryu:
  A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. 1-4
  
• Young-Ju Kim, Kyung-Hoon Lee, Seung-Hak Ji, Yi-Gi Kwon, Seung-Hoon Lee, Kyoung-Jun Moon, Michael Choi, Ho-Jin Park, Byeong-Ha Park:
  A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp. 1-4
  
• Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
  SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. 1-4
  

Modeling of Layout-Dependent Effects and RF Devices

• John Faricelli:
  Layout-dependent proximity effects in deep nanoscale CMOS. 1-8
  
• Sharad Kapur, David E. Long:
  Modeling of integrated RF passive devices. 1-8
  
• John Wood, Peter H. Aaen:
  On the modeling of LDMOS RF power transistors. 1-8
  

RF Power Amplifiers

• Peter J. Zampardi:
  Will CMOS amplifiers ever Kick-GaAs? 1-4
  
• Maryam Fathi, David K. Su, Bruce A. Wooley:
  A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS. 1-4
  
• Debopriyo Chowdhury, Lu Ye, Elad Alon, Ali M. Niknejad:
  A 2.4GHz mixed-signal polar power amplifier with low-power integrated filtering in 65nm CMOS. 1-4
  
• Ali Afsahi, Lawrence E. Larson:
  An integrated 33.5dBm linear 2.4GHz power amplifier in 65nm CMOS for WLAN applications. 1-4
  
• Andrea Pallotta, Wissam Eyssa, Luca Larcher, Riccardo Brama:
  Millimeter-wave 14dBm CMOS power amplifier with input-output distributed transformers. 1-4
  
• Tao-Yao Chang, Chao-Shiun Wang, Chorng-Kuang Wang:
  A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS. 1-4
  

Power Optimization and Multi-Processing for SoCs

• Chih-Chi Cheng, Yi-Min Tsai, Liang-Gee Chen, Anantha P. Chandrakasan:
  A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine. 1-4
  
• Wenyi Che, Dechao Meng, Xuegui Chang, Wei Chen, Lifang Wang, Yuqing Yang, Conghui Xu, Xi Tan, Na Yan, Hao Min:
  A semi-passive UHF RFID tag with on-chip temperature sensor. 1-4
  
• Seungjin Lee, Jinwook Oh, Minsu Kim, Junyoung Park, Joonsoo Kwon, Joo-Young Kim, Hoi-Jun Yoo:
  Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor. 1-4
  
• Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim:
  Reconfigurable mobile stream processor for ray tracing. 1-4
  
• Kwanyeob Chae, Saibal Mukhopadhyay, Chang-Ho Lee, Joy Laskar:
  A dynamic timing control technique utilizing time borrowing and clock stretching. 1-4
  

MM-Wave and Beyond

• Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda:
  A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. 1-4
  
• Hsieh-Hung Hsieh, Fu-Lung Hsueh, Chewnpu Jou, Fred Kuo, Sean Chen, Tzu-Jin Yeh, Kevin Kai-Wen Tan, Po-Yi Wu, Yu-Ling Lin, Ming-Hsien Tsai:
  A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS. 1-4
  
• Sujiang Rong, Howard C. Luong:
  V-band varactor-less interpolative-phase-tuning oscillators with multiphase outputs. 1-4
  
• Khoa M. Nguyen, Anthony Accardi, Helen Kim, Gregory W. Wornell, Charles Sodini:
  Digital phase tightening for millimeter-wave imaging. 1-4
  
• Joohwa Kim, Mehmet Parlak, James F. Buckwalter:
  A 77-GHz to 90-GHz bidirectional amplifier for half-duplex front-ends. 1-4
  
• Ruonan Han, Yaming Zhang, Dominique Coquillat, Julie Hoy, Hadley Videlier, Wojciech Knap, Elliott Brown, K. O. Kenneth:
  280-GHz schottky diode detector in 130-nm digital CMOS. 1-4
  

Luncheon Keynote

• Ian Wright:
  From pistons and gears to electronics and software: The coming transportation technology disruption. 1
  

Poster Session

• Aritra Dey, Hongjiang Song, Tofayel Ahmed, Sameer M. Venugopal, David R. Allee:
  Amorphous silicon 7 bit digital to analog converter on PEN. 1-4
  
• Siew-Seong Tan, Cheng-Yen Liu, Li-Ken Yeh, Yi-Hsiang Chiu, Michael S.-C. Lu, Klaus Y. J. Hsu:
  Design of low-noise CMOS MEMS accelerometer with techniques for thermal stability and stable DC biasing. 1-4
  
• Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic:
  A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors. 1-4
  
• Hossein Fariborzi, Matthew Spencer, Vaibhav Karkare, Jaeseok Jeon, Rhesa Nathanael, Chengcheng Wang, Fred Chen, Hei Kam, Vincent Pott, Tsu-Jae King Liu, Elad Alon, Vladimir Stojanovic, Dejan Markovic:
  Analysis and demonstration of MEM-relay power gating. 1-4
  
• Xiaoyu Zhang, Hanjun Jiang, Fule Li, Songyuan Cheng, Chun Zhang, Zhihua Wang:
  An energy-efficient SoC for closed-loop medical monitoring and intervention. 1-4
  
• Junhyeok Yang, Seungchul Jung, Young-Jin Woo, Jinyong Jeon, Sungwoo Lee, Changbyung Park, Hyunsik Kim, Seung-Tak Ryu, Gyu-Hyeong Cho:
  A novel readout IC with high noise immunity for charge-based touch screen panels. 1-4
  
• Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky:
  Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. 1-4
  
• David E. Duarte, Paola Zepeda, Suching Hsu, Atul Maheshwari, Greg Taylor:
  HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system. 1-4
  
• Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith E. Holbert:
  Single event transient mitigation in cache memory using transient error checking circuits. 1-4
  
• Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
  Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. 1-4
  
• Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De:
  Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. 1-4
  
• Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Qadeer Khan, Pavan Kumar Hanumolu:
  A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction. 1-4
  
• Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
  0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. 1-4
  
• Huanhuan Zou, Jun Liu, Jincai Wen, Huang Wang, Lingling Sun, Zhiping Yu:
  A novel wideband 1-π model with accurate substrate modeling for on-chip spiral inductors. 1-4
  
• Xin Pan, Helmut Graeb:
  Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction. 1-4
  
• Xia Li, Peter G. M. Baltus, Paul T. M. van Zeijl, Dusan M. Milosevic, Arthur H. M. van Roermund:
  A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology. 1-4
  
• Hiroshi Akima, Aleksander Dec, Timothy Merkin, Kenji Suyama:
  A 10 GHz frequency-drift temperature compensated LC VCO with fast-settling low-noise voltage regulator in 0.13 µm CMOS. 1-4
  
• Roc Berenguer, Gui Liu, Abe Akhiyat, Keya Kamtikar, Yang Xu:
  A 43.5mW 77GHz receiver front-end in 65nm CMOS suitable for FM-CW Automotive Radar. 1-4
  
• Hyunwon Moon, Seung-Chan Heo, Hwayeal Yu, Jinhyuck Yu, Ji-Soo Chang, Seung-Il Choi, Sangyoub Lee, Woo-Seung Choo, Byeong-Ha Park:
  A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS. 1-4
  
• Ming-Yeh Hsu, Chao-Shiun Wang, Chorng-Kuang Wang:
  A low power high reliability dual-path noise-cancelling LNA for WSN applications. 1-4
  
• Ning Zhang, K. O. Kenneth:
  W-band pulsed radar receiver in low cost CMOS. 1-4
  
• Xiaojie Chu, Min Lin, Zheng Gong, Yin Shi, Fa Foster Dai:
  A CMOS programmable gain amplifier with a novel DC-offset cancellation technique. 1-4
  
• Le Wang, Luke Theogarajan:
  A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systems. 1-4
  
• Ganesh K. Balachandran, Venkatesh Srinivasan, Vijay Rentala, Srinath Ramaswamy:
  A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter. 1-4
  
• Sungwoo Lee, Kiduk Kim, Kyusung Park, Changbyung Park, Byunghun Lee, Jinyong Jeon, Seungchul Jung, Jin Huh, Junhyeok Yang, Hyunsik Kim, Gyu-Hyeong Cho:
  A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control. 1-4
  
• Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon:
  A 9.15mW 0.22mm² 10b 204MS/s pipelined SAR ADC in 65nm CMOS. 1-4
  
• Jian Xu, Xiaobo Wu, Hanqing Wang, Bill Liu, Menglian Zhao:
  A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator. 1-4
  
• Xiong Liu, Alan N. Willson Jr.:
  A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCO. 1-4
  
• Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
  Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. 1-4
  
• Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic:
  A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs. 1-4
  
• Yang Sun, Chang-Jin Jeong, In-Young Lee, Jeong-Seon Lee, Sang-Gug Lee:
  A 50-300-MHz low power and high linear active RF tracking filter for digital TV tuner ICs. 1-4
  
• Tae-Hwan Kim, In-Cheol Park:
  A 2.6Gb/s 1.56mm² near-optimal MIMO detector in 0.18µm CMOS. 1-4
  
• Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammed M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
  Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. 1-4
  
• Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
  A customized design of DRAM controller for on-chip 3D DRAM stacking. 1-4
  
• Joseph F. Ryan, Benton H. Calhoun:
  A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. 1-4
  
• Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  A 34.7-mW quad-core MIQP solver processor for robot control. 1-4
  
• Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy:
  Data-dependant sense-amplifier flip-flop for low power applications. 1-4
  
• Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu:
  A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. 1-4
  
• Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park:
  A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. 1-4
  
• Mi-Jo Kim, Lee-Sup Kim:
  100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. 1-4
  
• Tzu-Chien Hsueh, Sudhakar Pamarti:
  A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment. 1-4
  
• David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor:
  Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. 1-4
  
• Heechai Kang, Kyungho Ryu, DongHwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung:
  Process variation tolerant all-digital multiphase DLL for DDR3 interface. 1-4
  
• Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony:
  Varactor-based signal restoration for near-speed-of-light surfing global interconnect. 1-4
  

Last update Thu May 24 02:41:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page