8. CHARME 1995:
: Describing and verifying synchronous circuits with the Boyer-Moore theorem prover.
: Problems encountered in the machine-assisted proof of hardware.
Formally verified synthesis
: A partial-order approach to the verification of concurrent systems: checking liveness properties.
Kees G. W. Goossens
: Reasoning about VHDL using operational and observational semantics.
: A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking.