Processor and memory architecture

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  Abhishek Deb, Josep M. Codina, Antonio González: SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. 1
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  Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik: Efficient stack distance computation for priority replacement policies. 2
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  Chunyang Gou, Georgi Gaydadjiev: Elastic pipeline: addressing GPU on-chip shared memory bank conflicts. 3

Performance evaluation and programming model

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  Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, Alexandru Nicolau: Pruning hardware evaluation space via correlation-driven application similarity analysis. 4
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  Socrates Demetriades, Sangyeun Cho: BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs. 5
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  Lingyuan Wang, Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi: Scaling scientific applications on clusters of hybrid multicore/GPU nodes. 6

Design for performance and resource efficiency

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  Josef Weidendorfer, Tilman Küstner, Sally A. McKee: Performance optimization by dynamic code transformation. 7
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  Emmanuel Arzuaga, David R. Kaeli: Increasing power/performance resource efficiency on virtualized enterprise servers. 8
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  Karthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham: A reconfigurable cache architecture for energy efficiency. 9
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  Karl-Filip Faxén, John Ardelius: Manycore work stealing. 10
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  Alessio Franceschelli, Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu, Martino Ruggiero, Michele Lombardi, Alessio Bonfietti, Michela Milano, Luca Benini: MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor. 11
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  Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero: Hybrid high-performance low-power and ultra-low energy reliable caches. 12
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  Ju-Young Jung, Sangyeun Cho: Dynamic co-management of persistent RAM main memory and storage resources. 13
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  Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Cluster-based topologies for 3D stacked architectures. 14
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  Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber: Maintaining real-time synchrony on SpiNNaker. 15

Architectural issues for multicore and multichip processing

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  Atsuya Okazaki, Yasunao Katayama, Seiji Munetoh: Universal optical multi-drop bus for heterogeneous memory architecture. 16
• 
  Victoria Caparrós Cabezas, Phillip Stanley-Marbell: Quantitative analysis of parallelism and data movement properties across the Berkeley computational motifs. 17
• 
  Riyaz Haque, David M. Peixotto, Vivek Sarkar: CnC-Hadoop: a graphical coordination language for distributed multiscale parallelism. 18
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  Francesca Palumbo, Danilo Pani, Andrea Deidda, Luigi Raffo: Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability. 19
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  Ahsan Shabbir, Sander Stuijk, Akash Kumar, Henk Corporaal, Bart Mesman: An MPSoC design approach for multiple use-cases of throughput constrainted applications. 20
• 
  Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang: AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. 21
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  Masana Murase, Hideaki Komatsu, Kumiko Maeda, Shigeho Noda, Munehiro Doi, Ryutaro Himeno: A parallel programming framework orchestrating multiple languages and architectures. 22
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  Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink: Composable local memory organisation for streaming applications on embedded MPSoCs. 23
• 
  Mouad Bahi, Christine Eisenbeis: Rematerialization-based register allocation through reverse computing. 24

Dynamic binary translation

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  Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura: On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. 25
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  Guilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang: Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. 26

Performance and parallelization tools

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  Ashwin M. Aji, Mayank Daga, Wu-chun Feng: Bounding the effect of partition camping in GPU kernels. 27
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  Romain Cledat, Kaushik Ravichandran, Santosh Pande: Leveraging data-structure semantics for efficient algorithmic parallelism. 28

Applications on multicore and accelerators

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  Alexander Heinecke, Dirk Pflüger: Multi- and many-core data mining with adaptive sparse grids. 29
• 
  Faizur Rahman, Qing Yi, Apan Qasem: Understanding stencil code performance on multicore architectures. 30
• 
  Sebastian Isaza, Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Georgi Gaydadjiev: Parametrizing multicore architectures for multiple sequence alignment. 31
• 
  Liu Peng, Aiichiro Nakano, Guangming Tan, Priya Vashishta, Dongrui Fan, Hao Zhang, Rajiv K. Kalia, Fenglong Song: Performance analysis and optimization of molecular dynamics simulation on Godson-T many-core processor. 32

Quantum computing, wireless networks, thread scheduling

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  Shruti Patil, David J. Lilja: Performing bitwise logic operations in cache using spintronics-based magnetic tunnel junctions. 33
• 
  Zhenbo Zhu, Parul Gupta, Qing Wang, Shivkumar Kalyanaraman, Yonghua Lin, Hubertus Franke, Smruti R. Sarangi: Virtual base station pool: towards a wireless network cloud for radio access networks. 34
• 
  Kishore Kumar Pusukuri, David Vengerov, Alexandra Fedorova, Vana Kalogeraki: FACT: a framework for adaptive contention-aware thread migrations. 35

Defect-tolerant design and security

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  Nawab Ali, Sriram Krishnamoorthy, Mahantesh Halappanavar, Jeff Daily: Tolerating correlated failures for generalized Cartesian distributions via bipartite matching. 36
• 
  Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri: SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. 37

Memory management, virtual machines and power consumption

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  Dong Li, Kirk W. Cameron, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz: Scalable memory registration for high performance networks using helper threads. 38
• 
  Hui Wang, Peter J. Varman: A flexible approach to efficient resource sharing in virtualized environments. 39
• 
  Arun Rangasamy, Y. N. Srikant: Evaluation of dynamic voltage and frequency scaling for stream programs. 40

last updated on Sat May 18 04:44:27 2013 by the dblp team
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