CASES 2011: Taipei, Taiwan
Rajesh K. Gupta, Vincent John Mooney (Eds.): Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011. ACM 2011 ISBN 978-1-4503-0713-0
Keynote address
- Arvind: Automatic generation of hardware/software interfaces. 1-2
Compiling and runtime support for mobile platforms
- Gernot Heiser: Low-overhead virtualization of mobile platforms. 3-4
- Seong-Won Lee, Soo-Mook Moon: Selective just-in-time compilation for client-side mobile javascript engine. 5-14
- Chih-Sheng Wang, Guillermo Pérez, Yeh-Ching Chung, Wei-Chung Hsu, Wei-Kuan Shih, Hong-Rong Hsu: A method-based ahead-of-time compiler for android applications. 15-24
Compiler smarts
- Quentin Colombet, Florian Brandner, Alain Darte: Studying optimal spilling in the light of SSA. 25-34
- Xuemeng Zhang, Hui Wu, Jingling Xue: An efficient heuristic for instruction scheduling on clustered vliw processors. 35-44
- Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello: Graph-coloring and treescan register allocation using repairing. 45-54
System software and memory architecture
- Eunjung Park, Sameer Kulkarni, John Cavazos: An evaluation of different modeling techniques for iterative compilation. 65-74
- Viswanath Krishnamurthy, Swamy D. Ponpandi, Akhilesh Tyagi: A novel thread scheduler design for polymorphic embedded systems. 75-84
Cache reliability
- Tayyeb Mahmood, Soontae Kim: Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers. 85-94
- Abbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt: FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation. 95-104
- Reiley Jeyapaul, Aviral Shrivastava: Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. 105-114
Safety and error tolerance
- Brett H. Meyer, Benton H. Calhoun, John Lach, Kevin Skadron: Cost-effective safety and fault localization using distributed temporal redundancy. 125-134
- John Sartori, Joseph Sloan, Rakesh Kumar: Stochastic computing: embracing errors in architectureand design of processors and applications. 135-144
Performance evaluation
- Alena Simalatsar, Yusi Ramadian, Kai Lampka, Simon Perathoner, Roberto Passerone, Lothar Thiele: Enabling parametric feasibility analysis in real-time calculus driven performance evaluation. 155-164
- Sascha Plazar, Jan C. Kleinsorge, Heiko Falk, Peter Marwedel: WCET-driven branch prediction aware code positioning. 165-174
Accelerated computing
- Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan: A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. 175-184
- Siddharth Nilakantan, Srikanth Annangi, Nikhil Gulati, Karthik Sangaiah, Mark Hempstead: Evaluation of an accelerator architecture for speckle reducing anisotropic diffusion. 185-194
- Ricardo S. Ferreira, Julio C. Goldner Vendramini, Lucas Mucida, Monica Magalhães Pereira, Luigi Carro: An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture. 195-204
Embedded multicore computing
- Adam R. Smith, Prasad A. Kulkarni: Localizing globals and statics to make C programs thread-safe. 205-214
- Ke Bai, Di Lu, Aviral Shrivastava: Vector class on limited local memory (LLM) multi-core processors. 215-224
Microfluidic biochips: recent research and emerging challenges
- Wajid Hassan Minhass, Paul Pop, Jan Madsen: System-level modeling and synthesis of flow-based microfluidic biochips. 225-234
Tutorials
- Sang Lyul Min, Eyee Hyun Nam: Hardware/software architecture for flash memory storage systems. 235-236
- Linh T. X. Phan, Insup Lee, Oleg Sokolsky: Compositional analysis of real-time embedded systems. 237-238
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last updated on 2013-06-17T203403 by the dblp team