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ORCID25th ASYNC 2019: Hirosaki, Japan
- 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019. IEEE 2019, ISBN 978-1-5386-4747-9
- Samira Ataei, Rajit Manohar:
AMC: An Asynchronous Memory Compiler. 1-8 - Adrian Mardari, Zuzana Jelcicová
, Jens Sparsø:
Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking. 9-18 - Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang:
Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. 19-26 - Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. 27-35 - Mackenzie J. Wibbels, Shomit Das, Dheeraj Singh Takur, Venkata Nori, Kenneth S. Stevens:
A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols. 36-45 - Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan:
Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone. 46-47 - Ziyang Kang, Lei Wang, Shasha Guo, Rui Gong, Yu Deng, Qiang Dou:
ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. 48-57 - Mickaël Fiorentino, Claude Thibeault, Yvon Savaria, François Gagnon, Tom Awad, Doug Morrissey, Michel Laurence:
AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. 58-59 - Alberto Moreno, Danil Sokolov, Jordi Cortadella:
Synthesis from Waveform Transition Graphs. 60-67 - Rajit Manohar, Yoram Moses:
Asynchronous Signalling Processes. 68-75 - Jürgen Maier, Matthias Függer, Thomas Nowak, Ulrich Schmid:
Transistor-Level Analysis of Dynamic Delay Models. 76-85 - Grégoire Gimenez, Jean Simatic, Laurent Fesquet:
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. 86-95 - Yan Peng, Mark R. Greenstreet:
Verifying Timed, Asynchronous Circuits using ACL2. 96-104 - Cuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland:
A Hierarchical Approach to Self-Timed Circuit Verification. 105-113 - Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans:
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. 114-123 - Jürgen Maier, Andreas Steininger:
Efficient Metastability Characterization for Schmitt-Triggers. 124-133 - Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai:
Hardware Trojan Insertion and Detection in Asynchronous Circuits. 134-143
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