Invited Talk 1

• 
  Robert P. Colwell: Deep Pipelines vs. Risk and Power Walls.

Circuit Techniques

• 
  Suwen Yang, Brian D. Winters, Mark R. Greenstreet: Energy Efficient Surfing. 2-11
• 
  Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland: GasP Control for Domino Circuits. 12-22
• 
  Tin Wai Kwan, Maitham Shams: Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. 23-32

On-Chip Networks

• 
  Tobias Bjerregaard, Jens Sparsø: A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip. 34-43
• 
  Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar: An Asynchronous Router for Multiple Service Levels Networks on Chip. 44-53
• 
  Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin: An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. 54-63

Clocking and Synchronization

• 
  Joep L. W. Kessels: Register Communication between Mutually Asynchronous Domains. 66-75
• 
  Milos Krstic, Eckhard Grass, Christian Stahl: Request-Driven GALS Technique for Wireless Communication System. 76-85
• 
  Scott Fairbanks, Simon W. Moore: Self-Timed Circuitry for Global Clocking. 86-96

Invited Talk 2

• 
  Robert J. Drost, Ivan E. Sutherland: Proximity Communication and Time.

Design Analysis

• 
  Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens: Modeling and Verifying Circuits Using Generalized Relative Timing. 98-108
• 
  Vassilis Zebilis, Christos P. Sotiriou: Controlling Event Spacing in Self-Timed Rings. 109-115
• 
  Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald: Delay Insensitive Encoding and Power Analysis: A Balancing Act. 116-125

Design Implementations

• 
  Justin Hensley, Anselmo Lastra, Montek Singh: A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. 128-137
• 
  Yee William Li, Kenneth L. Shepard, Yannis P. Tsividis: Continuous-Time Digital Signal Processors. 138-143
• 
  Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar: BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. 144-154

Test and Reliability

• 
  Wonjin Jang, Alain J. Martin: SEU-Tolerant QDI Circuits. 156-165
• 
  Frank te Beest, Ad M. G. Peeters: A Multiplexor Based Test Method for Self-Timed Circuits. 166-175

Invited Tutorial

• 
  Phillip Restle, Kenneth L. Shepard: New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems.

Encoding and Synthesis

• 
  Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers: High Level Synthesis of Timed Asynchronous Circuits. 178-189
• 
  Nikolai Starodoubtsev, Sergei Bystrov: Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. 190-200
• 
  Frederic Worm, Patrick Thiran, Paolo Ienne: A Unified Coding Framework for Delay-Insensitivity. 201-211

last updated on Wed May 22 04:20:02 2013 by the dblp team
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