Masaharu Imai (Ed.):
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004.
IEEE 2004, ISBN 0-7803-8175-0 Keynote address
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Rudy Lauwereins :
System level design technology for realizing an ambient intelligent environment.
1-3
Selected European activities in SoC low power design methodologies and research networking
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conf/aspdac/MarwedelWVSH04 export record as
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Wolfgang Nebel :
Predictable design of low power systems by pre-implementation estimation and optimization.
12-17
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Ahmed Amine Jerraya :
EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package.
18
Floorplanning
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Modeling for analog circuits
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Payam Heydari :
High-frequency noise in RF active CMOS mixers.
57-60
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Behavioral synthesis
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conf/aspdac/Najaf-Abadi04 Hashem Hashemi Najaf-abadi :
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline.
86-91
Delay test and BIST
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Embedded tutorial + regular session:
embedded szstem applications
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conf/aspdac/MaxiaguineKCT04
Placement
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conf/aspdac/EkpanyapongL04 export record as
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RF design methodology
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Practical issues in logic synthesis
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conf/aspdac/YoshikawaHKNIY04 export record as
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Effective test and diagnosis
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conf/aspdac/HayashiYSKT04 export record as
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System-level design methodology
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conf/aspdac/Schulz-KeyWSKR04 export record as
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conf/aspdac/DamaseviciusS04 export record as
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conf/aspdac/MuraokaNMYH04
Advanced design and modeling techniques
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Analog design and evaluation
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Jianhua Gan ,
Shouli Yan ,
Jacob A. Abraham :
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter.
292-297
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System design verification
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Miroslav N. Velev :
Efficient translation of boolean formulas to CNF in formal verification of microprocessors.
310-315
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Miroslav N. Velev :
Using positive equality to prove liveness for pipelined microprocessors.
316-321
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Opportunities with the open architecture test system
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Rochit Rajsuman :
New opportunities with the open architecture test system.
335
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Adi Merschon :
New opportunities with the open architecture test system.
341
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Tetsuo Tada :
Opportunities with the open architecture test system.
343
C-based design examples
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conf/aspdac/Wakabayashi04 Kazutoshi Wakabayashi :
C-based behavioral synthesis and verification analysis on industrial design examples.
344-348
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Buffered tree construction
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Jun Chen ,
Lei He :
Modeling of coplanar waveguide for buffered clock tree.
367-372
Power-aware approach for microprocessor design
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conf/aspdac/VivekanandarajahSB04 export record as
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conf/aspdac/BhattacharjeeP04
Analog layout techniques
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conf/aspdac/JangkrajarngBHS04 export record as
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conf/aspdac/BhattacharyaJHS04 export record as
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Formal verification
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conf/aspdac/ParthasarathyICW04 export record as
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Routing methodology
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Exploration for advanced SoC design
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Embedded software
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conf/aspdac/BouchhimaYJ04 export record as
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conf/aspdac/ShrivastavaD04 export record as
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Yoonseo Choi ,
Taewhan Kim :
Memory access driven storage assignment for variables in embedded system design.
478-481
RF modeling and design methodology
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conf/aspdac/Miura-Mattausch04 export record as
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Robert A. Mullen :
RF design methodologies bridging system-IC-module design.
491-498
Power grid analysis and design
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conf/aspdac/KurokawaOKM04
University design contest
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conf/aspdac/KurodaMMIHY04 export record as
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conf/aspdac/MiyamotoKMKO04 export record as
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conf/aspdac/UtsurogiHMT04 export record as
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conf/aspdac/SueyoshiUMKMH04 export record as
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conf/aspdac/KagawaKAIFON04 export record as
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conf/aspdac/OhkawaNFMLKKO04 export record as
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conf/aspdac/BalasundaramPPM04 export record as
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conf/aspdac/LeelarasmeeP04 export record as
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Hala A. Farouk ,
Magdy Saeb :
Design and implementation of a secret key steganographic micro-architecture employing FPGA.
577-578
Novel techniques in logic synthesis
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conf/aspdac/MartinelliKD04 export record as
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Future of ITS technologies in the ubiquitous society
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Naoki Tokitsu :
The integration of vehicles into a ubiquitous computing environment computing and networking technologies for vehicles.
604-608
Buffer planning
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Yi-Hui Cheng ,
Yao-Wen Chang :
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.
624-627
Design verification and simulation
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Task scheduling with DVS
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Dongkun Shin ,
Jihong Kim :
Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems.
653-658
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conf/aspdac/Gorji-AraCBRJ04 export record as
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Global routing
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Interconnect and ESD extraction
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Liu Yang ,
Xiaobo Guo ,
Zeyi Wang :
An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction.
702-706
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Reconfigurable systems
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Chi-Chou Kao ,
Yen-Tai Lai :
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction.
719-724
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HW/SW co-design
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DFM in Nm-process generation
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Shuji Tsukiyama :
Toward stochastic design for digital circuits: statistical static timing analysis.
762-767
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Louis Scheffer :
Physical CAD changes to incorporate design for lithography and manufacturability.
768-773
Advanced interconnect analysis
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Future reconfigurable computing system
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System-level architecture
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Embedded system architectures
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conf/aspdac/KobayashiKOSTI04
Crosstalk noise analysis
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Expressions for Boolean functions
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Semi-custom techniques in system design
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Yiran Chen ,
Kaushik Roy ,
Cheng-Kok Koh :
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
893-898
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