ASAP 2009: Boston, MA, USA

Arithmetic

• Tomás Lang, Alberto Nannarelli:
  Division Unit for Binary Integer Decimals. 1-7
  
• Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton:
  A Combined Decimal and Binary Floating-Point Multiplier. 8-15
  
• Jun Chen, James E. Stine:
  Parallel Prefix Ling Structures for Modulo 2^n-1 Addition. 16-23
  

FPGA Applications

• Weirong Jiang, Viktor K. Prasanna:
  A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification. 24-31
  
• Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor:
  Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. 32-37
  

Media and Image Processing

• Yangyang Pan, Tong Zhang:
  Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. 38-45
  
• Cor Meenderinck, Ben H. H. Juurlink:
  Specialization of the Cell SPE for Media Applications. 46-52
  
• Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar, Igor Durdanovic, Eric Cosatto, Hans Peter Graf:
  A Massively Parallel Coprocessor for Convolutional Neural Networks. 53-60
  

FPGA Applications II

• Seunghun Jin, Dongkyun Kim, Thuy Tuong Nguyen, Bongjin Jun, Daijin Kim, Jae Wook Jeon:
  An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map. 61-66
  
• Julien Lamoureux, Tony Field, Wayne Luk:
  Accelerating a Virtual Ecology Model with FPGAs. 67-74
  
• Junguk Cho, Bridget Benson, Shahnam Mirzaei, Ryan Kastner:
  Parallelized Architecture of Multiple Classifiers for Face Detection. 75-82
  

Arithmetic and Cryptography

• Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller:
  Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. 83-90
  
• Satyendra R. Datla, Mitchell A. Thornton, David W. Matula:
  A Low Power High Performance Radix-4 Approximate Squaring Circuit. 91-97
  
• Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Falko Strenzke:
  A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms. 98-105
  

Application-Specific Integrated Circuits

• Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, S. Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan:
  An Input Triggered Polymorphic ASIC for H.264 Decoding. 106-113
  
• Bassam Jamil Mohd, Earl E. Swartzlander Jr.:
  A Power-Scalable Switch-Based Multi-processor FFT. 114-120
  

Computational Biology

• Yongchao Liu, Bertil Schmidt, Douglas L. Maskell:
  MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA. 121-128
  
• Martin C. Herbordt, Md. Ashfaquzzaman Khan, Tony Dean:
  Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition. 129-136
  
• Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk:
  NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs. 137-144
  

Tools and Design Aids

• Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot:
  Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. 145-152
  
• Xavier Guerin, Frédéric Pétrot:
  A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs. 153-160
  
• Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich:
  Impact of Loop Tiling on the Controller Logic of Acceleration Engines. 161-168
  

Application-Specific Instruction Processors

• Christos Strydis, Georgi Gaydadjiev:
  Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors. 169-176
  
• Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic:
  Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. 177-182
  
• Arnaldo P. Azevedo Filho, Ben H. H. Juurlink:
  Scalar Processing Overhead on SIMD-Only Architectures. 183-190
  

Posters

• Mihaela Malita, Gheorghe Stefan:
  Integral Parallel Architecture & Berkeley's Motifs. 191-194
  
• Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani:
  Application Specific Transistor Sizing for Low Power Full Adders. 195-198
  
• Shafqat Khan, Emmanuel Casseau, Daniel Menard:
  Reconfigurable SWP Operator for Multimedia Processing. 199-202
  
• Raid Ayoub, Alex Orailoglu:
  Filtering Global History: Power and Performance Efficient Branch Predictor. 203-206
  
• Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata:
  Efficient Implementation of Carry-Save Adders in FPGAs. 207-210
  
• Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich:
  Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. 211-214
  
• Ray C. C. Cheung, Çetin Kaya Koç, John D. Villasenor:
  A High-Performance Hardware Architecture for Spectral Hash Algorithm. 215-218
  
• Lucas Vespa, Mini Mathew, Ning Weng:
  P3FSM: Portable Predictive Pattern Matching Finite State Machine. 219-222
  
• Yong-Joon Park, Zhao Zhang, Songqing Chen:
  Run-Time Detection of Malwares via Dynamic Control-Flow Inspection. 223-226
  
• Mao Nakajima, Minoru Watanabe:
  A 16-context Optically Reconfigurable Gate Array. 227-230
  
• Cao Liang, Xin-Ming Huang:
  Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture. 231-234
  
• Kai Zhang, Xinming Huang, Zhongfeng Wang:
  An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems. 235-238
  

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