ASAP 2008: Leuven, Belgium

Application-Specific Processor Instruction Sets

• Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
  Fast custom instruction identification by convex subgraph enumeration. 1-6
  
• Yedidya Hilewitz, Cédric Lauradoux, Ruby B. Lee:
  Bit matrix multiplication in commodity processors. 7-12
  

Interactive Session 1

• Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan:
  Synthesis of application accelerators on Runtime Reconfigurable Hardware. 13-18
  
• Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo:
  Floating point multiplication rounding schemes for interval arithmetic. 19-24
  
• Sundar Balasubramanian, Harold W. Carter, Andrey Bogdanov, Andy Rupp, Jintai Ding:
  Fast multivariate signature generation in hardware: The case of rainbow. 25-30
  
• Mohammad Hosseinabady, José L. Núñez-Yáñez:
  Fault-tolerant dynamically reconfigurable NoC-based SoC. 31-36
  
• Thomas Lorünser, Edwin Querasser, Thomas Matyus, Momtchil Peev, Johannes Wolkerstorfer, Michael Hutter, Alexander Szekely, Ilse Wimberger, Christian Pfaffel-Janser, Andreas Neppach:
  Security processor with quantum key distribution. 37-42
  
• Pramod Kumar Meher, Jagdish Chandra Patra:
  Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. 43-48
  
• Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy:
  Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. 49-54
  
• Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge:
  Run-time thread sorting to expose data-level parallelism. 55-60
  

System-level Interconnect and Mapping in SoCs

• Slavisa Jovanovic, Camel Tanougast, Serge Weber:
  A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems. 61-66
  
• David Dickin, Lesley Shannon:
  Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms. 67-72
  
• Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad:
  PERMAP: A performance-aware mapping for application-specific SoCs. 73-78
  

Advances in Cryptography

• Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, Siddika Berna Örs:
  Low-cost implementations of NTRU for pervasive security. 79-84
  
• Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, Ingrid Verbauwhede:
  On the high-throughput implementation of RIPEMD-160 hash algorithm. 85-90
  
• Haixin Wang, Guoqiang Bai, Hongyi Chen:
  Zodiac: System architecture implementation for a high-performance Network Security Processor. 91-96
  

New Computational Methods

• Pramod Kumar Meher:
  Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms. 97-101
  
• David B. Thomas, Wayne Luk:
  Resource efficient generators for the floating-point uniform and exponential distributions. 102-107
  
• Ishaan L. Dalal, Deian Stefan, Jared Harwayne-Gidansky:
  Low discrepancy sequences for Monte Carlo simulations on reconfigurable platforms. 108-113
  

Novel Applications

• Yves Vanderperren, Wim Dehaene:
  A subsampling pulsed UWB demodulator based on a flexible complex SVD. 114-119
  
• J. Divyasree, H. Rajashekar, Kuruvilla Varghese:
  Dynamically reconfigurable regular expression matching architecture. 120-125
  
• Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser:
  An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. 126-131
  

New Directions in Application-Specific Design

• Wangyuan Zhang, Tao Li:
  Managing multi-core soft-error reliability through utility-driven cross domain optimization. 132-137
  

Interactive Session 2

• Sherman Braganza, Miriam Leeser:
  An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. 138-143
  
• Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch:
  A parallel hardware architecture for connected component labeling based on fast label merging. 144-149
  
• Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
  Operation shuffling over cycle boundaries for low energy L0 clustering. 150-155
  
• Vamsi Kundeti, Yunsi Fei, Sanguthevar Rajasekaran:
  An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor. 156-161
  
• Basant K. Mohanty, Pramod Kumar Meher:
  Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. 162-166
  
• Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals, Richard E. Cagley:
  Design space exploration of a cooperative MIMO receiver for reconfigurable architectures. 167-172
  
• Mao Nakajima, Minoru Watanabe:
  Dynamic holographic reconfiguration on a four-context ODRGA. 173-178
  
• Fernando Pardo, Paula López Martinez, Diego Cabello:
  FPGA-based hardware accelerator of the heat equation with applications on infrared thermography. 179-184
  
• Masih Rahmaty, Mohammad S. Sadri, Mehdi Ataei Naeini:
  FPGA based singular value decomposition for image processing applications. 185-190
  

Acceleration of Scientific and DSP Applications

• Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain:
  Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. 191-196
  
• Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave:
  A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. 197-202
  
• Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk:
  Reconfigurable acceleration of microphone array algorithms for speech enhancement. 203-208
  

Advanced Communications Applications

• Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Cavallaro:
  Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. 209-214
  
• Marcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard Fettweis:
  Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. 215-220
  
• Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf:
  Buffer allocation for advanced packet segmentation in Network Processors. 221-226
  

Arithmetic

• Álvaro Vázquez, Elisardo Antelo:
  New insights on Ling adders. 227-232
  
• Nicolas Brisebarre, Sylvain Chevillard, Milos D. Ercegovac, Jean-Michel Muller, Serge Torres:
  An efficient method for evaluating polynomial and rational function approximations. 233-238
  
• Nicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller:
  Integer and floating-point constant multipliers for FPGAs. 239-244
  

Interconnect and Mapping

• Andres Garcia, Mladen Berekovic, Tom Vander Aa:
  Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor. 245-250
  
• Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan:
  RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. 251-256
  
• Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
  Loop-oriented metrics for exploring an application-specific architecture design-space. 257-262
  

Novel Processor and Memory System Techniques

• Santanu Kumar Dash, Thambipillai Srikanthan:
  Rapid estimation of instruction cache hit rates using loop profiling. 263-268
  
• Xuan Guan, Yunsi Fei:
  Reducing power consumption of embedded processors through register file partitioning and compiler support. 269-274
  
• Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
  Lightweight DMA management mechanisms for multiprocessors on FPGA. 275-280
  
• Pepijn J. de Langen, Ben H. H. Juurlink:
  Memory copies in multi-level memory systems. 281-286
  

Image and Video Processing

• Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan:
  Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. 287-292
  
• Roberto R. Osorio, Javier D. Bruguera:
  An FPGA architecture for CABAC decoding in manycore systems. 293-298
  
• Andre Guntoro, Manfred Glesner:
  Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. 299-304
  
• Basant K. Mohanty, Pramod Kumar Meher:
  Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. 305-309
  

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