ASAP 2005: Samos, Greece

Cover Pages

• Title Page.
  
• Copyright Page.
  

Introduction

• Message from the Conference Chairs.
  
• Conference Organizers.
  
• Program Committee.
  
• External Referees.
  

Keynote

• Michael J. Flynn:
  Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems. 3
  

Session 1: Codesign Specification and Synthesis

• Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich:
  Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. 9-14
  
• Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
  Expression Synthesis in Process Networks generated by LAURA. 15-21
  
• Bharath N, Nagaraju Bussa:
  Artificial Deadlock Detection in Process Networks for ECLIPSE. 22-27
  
• Alain Darte, Steven Derrien, Tanguy Risset:
  Hardware/Software Interface for Multi-Dimensional Processor Arrays. 28-35
  
• Kiyofumi Tanaka:
  Casablanca II: Implementation of a Real-Time RISC. 36-42
  
• Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere:
  Behavioral specification of control interface for signal processing applications. 43-49
  
• Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis:
  Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. 50-59
  
• Karim Ben Chehida, Michel Auguin:
  A SW/Configware Codesign Methodology for Control Dominated Applications. 56-64
  

Session 2: (Special) System Level Soc Design

• Samarjit Chakraborty:
  Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing. 65-72
  
• Ümit Y. Ogras, Jingcao Hu, Radu Marculescu:
  Communication-Centric SoC Design for Nanoscale Domain. 73-78
  
• Sudeep Pasricha, Mohamed Ben-Romdhane:
  Using TLM for Exploring Bus-based SoC Communication Architectures. 79-85
  
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti:
  Exploring Design Space of VLIW Architectures. 86-91
  
• Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev:
  The Midlifekicker Microarchitecture Evaluation Metric. 92-100
  

Session 3: Applications

• Jayaprakash Pisharath, Alok N. Choudhary:
  Design of a Hardware Accelerator for Density Based Clustering Applications. 101-106
  
• Adrian Burian, Perttu Salmela, Jarmo Takala:
  Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture. 107-112
  
• Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai:
  A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor. 113-118
  
• Enrico Ng, Gyungho Lee:
  Eliminating Sorting in IP Lookup Devices using Partitioned Table. 119-126
  

Session 4: Architectures, ISA & Microarchitecture

• Ludovic L'Hours:
  Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications. 127-133
  
• Moboluwaji O. Sanu, Earl E. Swartzlander Jr.:
  Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. 134-139
  
• Nikolaos Kavvadias, Spiridon Nikolaidis:
  Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding. 140-145
  
• Jan-Willem van de Waerdt, Stamatis Vassiliadis:
  Instruction Set Architecture Enhancements for Video Processing. 146-153
  
• Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers:
  Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. 154-160
  
• Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis:
  Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. 161-168
  
• Byeong Kil Lee, Lizy Kurian John, Eugene John:
  Architectural Support for Accelerating Congestion Control Applications in Network Processors. 169-178
  

Session 5: Power Aware Systems & VLSI CAD

• Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina:
  Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. 179-184
  
• Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou:
  A Low-Power Processor Architecture Optimized forWireless Devices. 185-190
  
• Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu:
  CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems. 191-197
  
• Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan:
  Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. 198-203
  
• Thi Nguyen, Kaijian Shi:
  Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. 204-212
  

Session 6: (Special) Reconfigurable Computing

• Christian Plessl, Marco Platzner:
  Zippy - A coarse-grained reconfigurable array with support for hardware virtualization. 213-218
  
• Amilcar do Carmo Lucas, Rolf Ernst:
  An Image Processor for Digital Film. 219-224
  
• João M. P. Cardoso:
  On Estimations for Compiling Software to FPGA-based Systems. 225-230
  
• Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka:
  A Programmable DSP Architecture for Wireless Communication Systems. 231-238
  
• Andreas Fidjeland, Wayne Luk:
  Customising Application-Speci.c Multiprocessor Systems: a Case Study. 239-246
  

Session 7: (Special) Nanocomputing

• Jie Han, Erin Taylor, Jianbo Gao, José A. B. Fortes:
  Faults, Error Bounds and Reliability of Nanoelectronic Circuits. 247-253
  
• Maria J. Avedillo, José M. Quintana, Héctor Pettenghi:
  Logic Models Supporting the Design of MOBILE-based RTD Circuits. 254-259
  
• Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio:
  CONAN - A Design Exploration Framework for Reliable Nano-Electronics. 260-267
  
• Bjørn Jager, Jörg-Christian Niemann, Ulrich Rückert:
  Analytical approach to massively parallel architectures for nanotechnologies. 268-275
  
• Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal:
  On the Advantages of Serial Architectures for Low-Power Reliable Computations. 276-281
  
• Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire:
  Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems. 282-287
  
• Konrad Walus, Mike Mazur, Gabriel Schulhof, Graham A. Jullien:
  Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA). 288-293
  
• Cor Meenderinck, Sorin Cotofana, Casper Lageweg:
  High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. 294-302
  

Session 8: Arithmetic

• Jean-Luc Beuchat, Jean-Michel Muller:
  Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. 303-308
  
• Liang-Kai Wang, Michael J. Schulte:
  Decimal Floating-Point Square Root Using Newton-Raphson Iteration. 309-315
  
• Milos D. Ercegovac, Jean-Michel Muller:
  Variable Radix Real and Complex Digit-Recurrence Division. 316-321
  
• Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata:
  On-line Multioperand Addition Based on On-line Full Adders. 322-327
  
• Jérémie Detrey, Florent de Dinechin:
  Table-based polynomials for fast hardware function evaluation. 328-333
  
• Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
  Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x. 334-342
  

Session 9: Cryptography and Coding

• Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta:
  Architectural Extensions for Elliptic Curve Cryptography over GF(2^m) on 8-bit Microprocessors. 343-349
  
• Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede:
  Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2ⁿ). 350-355
  
• A. Murat Fiskiran, Ruby B. Lee:
  On-Chip Lookup Tables for Fast Symmetric-Key Encryption. 356-363
  
• Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner:
  Instruction Set Extensions for Reed-Solomon Encoding and Decoding. 364-369
  
• Perttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala:
  256-State Rate 1/2 Viterbi Decoder on TTA Processor. 370-378
  

Session 10: Signal and Video Processing

• M. Van Der Horst, Kees van Berkel, Johan Lukkien, Rudolf H. Mak:
  Recursive Filtering on a Vector DSP with Linear Speedup. 379-386
  
• Ian Steiner, P. Chan, Laurent Imbert, Graham A. Jullien, Vassil S. Dimitrov, G. H. McGibney:
  A Fault-Tolerant Modulus Replication Complex FIR Filter. 387-392
  
• Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
  Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform. 393-398
  
• Michael T. Frederick, Nathan A. VanderHorn, Arun K. Somani:
  Real-time H/W Implementation of the Approximate Discrete Radon Transform. 399-404
  
• Tom R. Jacobs, José L. Núñez-Yáñez:
  A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. 405-410
  
• José L. Núñez-Yáñez, Vassilios A. Chouliaras:
  Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. 411-416
  

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