ASAP 2004: Galveston, TX, USA

@proceedings{DBLP:conf/asap/2004,
  title     = {15th  IEEE International Conference on Application-Specific Systems,
               Architectures, and Processors (ASAP 2004), 27-29 September 2004,
               Galveston, TX, USA},
  booktitle = {ASAP},
  publisher = {IEEE Computer Society},
  year      = {2004},
  isbn      = {0-7695-2226-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Scheduling and Codesign

• François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner:
  Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations. 6-16
  
• Frank Hannig, Jürgen Teich:
  Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. 17-27
  
• Vida Kianzad, Shuvra S. Bhattacharyya:
  CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems. 28-40
  
• Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Reliability-Aware Co-Synthesis for Embedded Systems. 41-50
  

Arithmetic I

• Milos D. Ercegovac, Jean-Michel Muller:
  Complex Square Root with Operand Prescaling. 52-62
  
• Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase:
  Parallel Montgomery Multipliers. 63-72
  
• Alexandre F. Tenca, Ajay C. Shantilal, Mohammed H. Sinky:
  Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications. 73-83
  
• Liang-Kai Wang, Michael J. Schulte:
  Decimal Floating-Point Division Using Newton-Raphson Iteration. 84-95
  

Instruction Set Extensions

• Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram:
  A Public-Key Cryptographic Processor for RSA and ECC. 98-110
  
• Johann Großschädl, Sandeep S. Kumar, Christof Paar:
  Architectural Support for Arithmetic in Optimal Extension Fields. 111-124
  
• A. Murat Fiskiran, Ruby B. Lee:
  Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields. 125-136
  
• Jongmyon Kim, D. Scott Wills:
  Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems. 137-149
  

(Special) Nanocomputing

• Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
  Binary Multiplication based on Single Electron Tunneling. 152-166
  
• Valeriu Beiu:
  A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. 167-177
  

Microarchitecture, Compilers and Optimization

• Rama Sangireddy:
  Register Organization for Enhanced On-Chip Parallelism. 180-190
  
• Ljiljana Dilparic, D. K. Arvind:
  Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices. 191-201
  
• Anup Hosangadi, Farzan Fallah, Ryan Kastner:
  Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis. 202-212
  
• José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor:
  Optimizing the Memory Bandwidth with Loop Morphing. 213-223
  
• Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha:
  Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. 224-234
  

Arithmetic II

• Alex Fit-Florea, David W. Matula:
  A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2^k. 236-246
  
• Lo'ai Ali Tawalbeh, Alexandre F. Tenca:
  An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2ⁿ). 247-257
  
• Luca Breveglieri, Israel Koren, Paolo Maistri:
  Detecting Faults in Four Symmetric Key Block Ciphers. 258-268
  
• Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis:
  A Low-Power Carry Skip Adder with Fast Saturation. 269-279
  

Communication, Interfaces and Memory

• Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
  A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. 282-292
  
• Antoine Fraboulet, Tanguy Risset:
  Efficient On-Chip Communications for Data-Flow IPs. 293-303
  
• Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke:
  Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. 304-314
  
• Sebastian Siegel, Renate Merker:
  Optimized Data-Reuse in Processor Arrays. 315-325
  

(Special) Reconfigurable Computing

• Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni:
  Hyper-Programmable Architectures for Adaptable Networked Systems. 328-338
  
• Miljan Vuletic, Laura Pozzi, Paolo Ienne:
  Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. 339-351
  

Applications

• Tom Van Court, Martin C. Herbordt:
  Families of FPGA-Based Algorithms for Approximate String Matching. 354-364
  
• Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster:
  Biosequence Similarity Search on the Mercury System. 365-375
  
• Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala:
  Stride Permutation Networks for Array Processors. 376-386
  
• Fabien Castanier, Alberto Ferrante, Vincenzo Piuri:
  A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems. 387-397
  
• Oliver Amft, Michael Lauffer, Stijn Ossevoort, Fabrizio Macaluso, Paul Lukowicz, Gerhard Tröster:
  Design of the QBIC Wearable Computing Platform. 398-410
  

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