ASAP 1997: Zurich, Switzerland

@proceedings{DBLP:conf/asap/1997,
  title     = {1997 International Conference on Application-Specific Systems,
               Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich,
               Switzerland},
  publisher = {IEEE Computer Society},
  year      = {1997},
  isbn      = {0-8186-7958-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote

• Michael Zeller, James C. Phillips, A. Dalke, W. Humphrey, Klaus Schulten, Thomas S. Huang, Vladimir Pavlovic, Yunxin Zhao, Zion Lo, Stephen M. Chu, Rajeev Sharma:
  A Visual Computing Environment for Very Large Scale Biomolecular Modeling. 3-
  

Regular Architectures

• Vwani P. Roychowdhury, M. P. Anantram:
  On Computing With Locally-Interconnected Architectures in Atomic/Nanoelectronic Systems. 14-23
  
• Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.:
  Realization of a nonlinear digital filter on a DSP array processor. 24-33
  
• Hyunman Chang, Soohwan Ong, Myung Hoon Sunwoo:
  A Linear Array Parallel Image Processor: SliM-II. 34-41
  
• D. Noguet:
  A massively parallel implementation of the watershed based on cellular automata. 42-52
  
• Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma:
  A strategy for determining a Jacobi specific dataflow processor. 53-
  

Architectures for Video Coding

• Eddy de Greef, Francky Catthoor, Hugo De Man:
  Array Placement for Storage Size Reduction in Embedded Multimedia Systems. 66-75
  
• Yuan-Hau Yeh, Chen-Yi Lee:
  Buffer size optimization for full-search block matching algorithms. 76-85
  
• Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet:
  A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor. 86-95
  
• Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee:
  A flexible data-interlacing architecture for full-search block-matching algorithm. 96-
  

Arithmetic

• Roberto R. Osorio, Javier D. Bruguera:
  New arithmetic coder/decoder architectures based on pipelining. 106-115
  
• Ansgar Drolshagen, H. Henkelmann, Walter Anheier:
  Processor Elements for the Standard Cell Implementation of Residue Number Systems. 116-123
  
• Julio Villalba, Tomás Lang:
  Low latency word serial CORDIC. 124-131
  
• Tomás Lang, Elisardo Antelo:
  CORDIC-based computation of arccos and arcsin. 132-143
  
• Michael J. Schulte, James E. Stine:
  Accurate Function Approximations by Symmetric Table Lookup and Addition. 144-153
  
• Christian V. Schimpfle, Sven Simon, Josef A. Nossek:
  Low Power CORDIC Implementation Using Redundant Number Representation. 154-161
  
• B. Haller, J. Goetze, Joseph R. Cavallaro:
  Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering. 162-
  

Keynote

• Luc Bougé, David Cachera:
  A logical framework to prove properties of Alpha programs. 187-198
  
• Dirk Fimmel, Renate Merker:
  Determination of the Processor Functionality in the Design of Processor Arrays. 199-208
  
• Rumen Andonov, Nicola Yanev, Hafid Bourzoufi:
  Three-dimensional orthogonal tile sizing problem: mathematical programming approach. 209-218
  
• Uwe Eckhardt, Renate Merker:
  Scheduling in Co-Partitioned Array Architectures. 219-228
  
• Pierre-Yves Calland, Jack Dongarra, Yves Robert:
  Tiling with limited resources. 229-238
  
• Florent de Dinechin:
  Libraries of schedule-free operators in Alpha. 239-
  

Mapping Models of Computation to Architectures

• Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee:
  Optimized software synthesis for synchronous dataflow. 250-262
  
• Richard S. Stevens:
  The Processing Graph Method Tool (PGMT). 263-271
  
• Helvio P. Peixoto, Margarida F. Jacome:
  Algorithm and architecture-level design space exploration using hierarchical data flows. 272-282
  
• Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr:
  Mapping multirate dataflow to complex RT level hardware models. 283-
  

Design Methodology I

• Carsten Reuter, Markus Schwiegershausen, Peter Pirsch:
  Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. 294-303
  
• Dolors Royo, Miguel Valero-García, Antonio González, Carme Mari:
  A Methodology for User-Oriented Scalability Analysis. 304-315
  
• Terry Disz, Robert Olson, Rick L. Stevens:
  Performance model of the Argonne Voyager multimedia server. 316-327
  
• Jian Chen, Valerie E. Taylor:
  PART: a partitioning tool for efficient use of distributed systems. 328-337
  
• Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf:
  An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. 338-349
  
• Corinne Ancourt, Denis Barthou, Christophe Guettier, François Irigoin, Bertrand Jeannet, Jean Jourdan, Juliette Mattioli:
  Automatic data mapping of signal processing applications. 350-
  

Keynote

• Carl Ebeling, Darren C. Cronquist, Paul Franklin:
  Configurable computing: the catalyst for high-performance architectures. 364-373
  
• Luca Breveglieri, Luigi Dadda, Vincenzo Piuri:
  Fast Arithmetic and Fault Tolerance in the FERMI System. 374-383
  
• M. Cavadini, M. Wosnitza, Markus Thaler, Gerhard Tröster:
  A Multiprocessor System for Real Time High Resolution Image Correlation. 384-391
  
• Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
  A Novel Sequencer Hardware for Application Specific Computing. 392-401
  
• Cristiano C. de Araujo, Marcus V. D. dos Santos, Edna Barros:
  A FPGA-based Implementation of an Intravenous Infusion Controller System. 402-411
  
• Stephanie Dogimont, M. Gumm, Friederich Mombers, Daniel Mlynek, A. Torielli:
  Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. 412-421
  
• Andy Negoi, Alain Guyot, Jacques Zimmermann:
  A dedicated circuit for charged particles simulation using the Monte Carlo method. 422-431
  
• Mike Parks:
  A Modular Element for Shared Buffer ATM Switch Fabrics. 432-
  

Design Methodology II

• Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll:
  A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. 438-447
  
• Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr:
  On core and more: a design perspective for systems-on-a-chip. 448-457
  
• Herbert Dawid, Klaus-Jürgen Koch, Johannes Stahl:
  ADPCM codec: from system level description to versatile HDL model. 458-467
  
• Gerhard Fettweis:
  Design methodology for digital signal processing. 468-
  

Image Processing and Filtering

• Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele:
  A flexible VLSI architecture for variable block size segment matching with luminance correction. 479-488
  
• Peter Rieder, Josef A. Nossek:
  Implementation of Orthogonal Wavelet Transforms and their Applications. 489-498
  
• Manuel Sánchez, Juan López, Oscar G. Plata, Emilio L. Zapata:
  An efficient architecture for the in place fast cosine transform. 499-508
  
• Jui-Hua Li, Nam Ling:
  An efficient video decoder design for MPEG-2 MP@ML. 509-518
  
• Christian Luetkemeyer:
  An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers. 519-528
  
• Benjamin W. Wah, Yi Shang, Zhe Wu:
  Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks. 529-
  

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