ASAP 1995: Strasbourg, France

@proceedings{DBLP:conf/asap/1995,
  title     = {The International Conference on Application Specific Array Processors
               (ASAP'95), July 24-26, 1995, Strasbourg, France},
  publisher = {IEEE Computer Society},
  year      = {1995},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Scheduling and Mapping

• Doran Wilde, Sanjay V. Rajopadhye:
  The naive execution of affine recurrence equations. 1-12
  
• Alain Darte, Frédéric Vivien:
  Revisiting the Decomposition of Karp, Miller and Winograd. 13-25
  
• Chris J. Scheiman, Peter R. Cappello:
  A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms. 26-33
  
• Hyuk-Jae Lee, José A. B. Fortes:
  Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms. 34-
  

Architectures I

• Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Larry Wilson:
  Time-optimal ranking algorithms on sorted matrices. 42-53
  
• Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri:
  Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. 54-65
  
• Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee:
  Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor. 66-75
  
• Anders Kugler, Roger D. Hersch:
  A Scalable Halftoning Coprocessor Architecture. 76-84
  
• Paolo Ienne:
  Horizontal Microcode Compaction for Programmable Systolic Accelerators. 85-
  

Arithmetic I

• Luca Breveglieri, Luigi Dadda, Vincenzo Piuri:
  Column Compression Pipelined Multipliers. 93-103
  
• Michael J. Schulte, Earl E. Swartzlander Jr.:
  A Processor for Staggered Interval Arithmetic. 104-112
  
• Rong Lin, Stephan Olariu:
  A simple array processor for binary prefix sums. 113-
  

Poster Presentations

• Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
  The MGAP's programming environment and the *C++ language. 121-124
  
• B. Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis:
  The VLSI design and implementation of the array processors of a multilayer vision system architecture. 125-128
  
• Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
  A Parallelizing Compilation Method for the Map-oriented Machine. 129-132
  
• Amar Mukherjee, Tinku Acharya:
  VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes. 133-136
  
• Richard Hughey:
  Parallel Sequence Comparison and Alignment. 137-140
  
• D. W. Brown, F. M. F. Gaston:
  The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs. 141-
  

Signal and Image Processing

• Pascale Guerdoux-Jamet, Dominique Lavenier:
  Systolic Filter for Fast DNA Similarity Search. 145-156
  
• Thomas Alexander, John L. Ellis, Gershon Kedem:
  A Solid Translation Engine using Ray Representation. 157-165
  
• Robert Lang, Andrew Spray:
  Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet Transform. 166-173
  
• Jongwoo Bae, Viktor K. Prasanna:
  Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms. 174-
  

Motion Estimation

• Pierpaolo Baglietto, Massimo Maresca, A. Migliaro, Mauro Migliardi:
  Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation. 182-192
  
• Ronan Barzic, Christian Bouville, François Charot, Gwendal Le Fol, Pascal Lemonnier, Charles Wagner:
  MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms. 193-203
  
• Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
  Motion Estimation Algorithms on Fine Grain Array Processor. 204-213
  
• Yin Chan, Sun-Yuan Kung:
  Bit Level Block Matching Systolic Arrays. 214-
  

Architecture II

• Zhan Chen, Israel Koren:
  Techniques for Yield Enhancement of VLSI Adders. 222-229
  
• Joseph A. Fernando, Jack S. N. Jean:
  Interfacing FPGA/VLSI Processor Arrays. 230-237
  
• Richard K. Squier, Kenneth Steiglitz, Mariusz H. Jakubowski:
  Implementation of Parallel Arithmetic in a Cellular Automaton. 238-
  

Arithmetic II

• Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
  Digit On-line Large Radix CORDIC Rotator. 246-257
  
• Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
  CORDIC Architectures with Parallel Compensation of the Scale Factor. 258-269
  
• Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, William C. Miller, Zhongde Wang:
  An array processor for inner product computations using a Fermat number ALU. 270-281
  
• Tudor Jebelean:
  Design of a systolic coprocessor for rational addition. 282-289
  
• Valentina P. Markova:
  Multilayer Cellular Algorithm for Complex Number Multiplication. 290-
  

Design Methodologies

• Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee:
  Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. 298-309
  
• Patrick M. Lenders, Sanjay V. Rajopadhye:
  Synthesis of Multirate VLSI Arrays. 310-321
  
• Gérard Ramstein, Olivier Déforges, P. Bakowski:
  A Design Tool for the Specification and the Simulation of Array Processors Architectures - Application to Image Processing: The Extraction of Regions of Interests. 322-329
  
• Pierre-Yves Calland, Tanguy Risset:
  Precise Tiling for Uniform Loop Nests. 330-
  

Last update Tue May 22 23:22:52 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page