24. ARCS 2011: Como, Italy

Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano (Eds.): Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings. Lecture Notes in Computer Science 6566 Springer 2011, ISBN 978-3-642-19136-7

Customization and Application Speci.c Accelerators

Volker Hampel, Grigori Goronzy, Erik Maehle:
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems. 1-12
Catalin Bogdan Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramírez, Georgi Gaydadjiev:
Scalability Evaluation of a Polymorphic Register File: A CG Case Study. 13-25
Antonino Tumeo, Simone Secchi, Oreste Villa:
Experiences with String Matching on the Fermi Architecture. 26-37

Hao Shen, Frédéric Pétrot:
Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors. 38-49
Yuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa:
Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore Environment. 50-61
Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. 62-73

Matteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto:
Emulating Transactional Memory on FPGA Multiprocessors. 74-85
Jörg Sachße, Heinz-Dietrich Wuttke, Steffen Ostendorff, Jorge H. Meza Escobar:
Architecture of an Adaptive Test System Built on FPGAs. 86-97
Angham A. Sabagh, Adil Al-Yasiri:
An Extensible Framework for Context-Aware Smart Environments. 98-109

Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout:
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3. 110-121
Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer:
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware. 122-134
Marius Grannæs, Magnus Jahre, Lasse Natvig:
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. 135-146

Martin Schindewolf, Alexander Esselson, Wolfgang Karl:
Compiler-Assisted Selection of a Software Transactional Memory System. 147-157
Arnaldo Azevedo, Ben H. H. Juurlink:
An Instruction to Accelerate Software Caches. 158-170
Pedro Trancoso, Norbert Martínez-Bazan, Josep-Lluis Larriba-Pey:
Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload. 171-182

David Kramer, Rainer Buchty, Wolfgang Karl:
A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systems. 183-194
Michael Wittke, Carsten Grenz, Jörg Hähner:
Towards Organic Active Vision Systems for Visual Surveillance. 195-206
Kamil Kloch, Gerald Pirkl, Paul Lukowicz, Carl Fischer:
Emergent Behaviour in Collaborative Indoor Localisation: An Example of Self-organisation in Ubiquitous Sensing Systems. 207-218

Son Truong Nguyen, Shigeru Oyanagi:
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation. 219-230
Nasibeh Teimouri, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad:
Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths. 231-242
Oscar Almer, Nigel P. Topham, Björn Franke:
A Learning-Based Approach to the Automated Design of MPSoC Networks. 243-258
Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich:
Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa. 259-270

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