23. ARCS 2010: Hannover, Germany

Keynote

• Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili:
  HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. 1
  

Processor Design

• Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer:
  How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT. 2-14
  
• Görkem Asilioglu, Emine Merve Kaya, Oguz Ergin:
  Complexity-Effective Rename Table Design for Rapid Speculation Recovery. 15-24
  
• Thomas B. Preußer, Peter Reichel, Rainer G. Spallek:
  An Embedded GC Module with Support for Multiple Mutators and Weak References. 25-36
  

Embedded Systems

• Patrick Bellasi, William Fornaciari, David Siorpaes:
  A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems. 37-48
  
• Johannes Zeppenfeld, Andreas Herkersdorf:
  Autonomic Workload Management for Multi-core Processor Systems. 49-60
  
• Bojan Jakimovski, Benjamin Meyer, Erik Maehle:
  Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture. 61-72
  

Organic Computing and Self-organization

• Matthias Bonn, Hartmut Schmeck:
  The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments. 73-86
  
• Jan-Philipp Steghöfer, Pratik Mandrekar, Florian Nafz, Hella Seebach, Wolfgang Reif:
  On Deadlocks and Fairness in Self-organizing Resource-Flow Systems. 87-100
  
• Kamil Kloch, Jan W. Kantelhardt, Paul Lukowicz, Patrick Wüchner, Hermann de Meer:
  Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems. 101-112
  

Processor Design and Transactional Memory

• Pavlos Petoumenos, Georgia Psychou, Stefanos Kaxiras, Juan Manuel Cebrian Gonzalez, Juan L. Aragón:
  MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance. 113-125
  
• Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero:
  Exploiting Inactive Rename Slots for Detecting Soft Errors. 126-137
  
• Yi Liu, Yangming Su, Cui Zhang, Mingyu Wu, Xin Zhang, He Li, Depei Qian:
  Efficient Transaction Nesting in Hardware Transactional Memory. 138-149
  

Energy Management in Distributed Environments and Ad-Hoc Grids

• Birger Becker, Florian Allerding, Ulrich Reiner, Mattias Kahl, Urban Richter, Daniel Pathmaperuma, Hartmut Schmeck, Thomas Leibfried:
  Decentralized Energy-Management to Control Smart-Home Architectures. 150-161
  
• Manuel F. Dolz, Juan Carlos Fernández, Rafael Mayo, Enrique S. Quintana-Ortí:
  EnergySaving Cluster Roll: Power Saving System for Clusters. 162-173
  
• Tariq Abdullah, Koen Bertels, Luc Onana Alima, Zubair Nawaz:
  Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids. 174-186
  

Performance Modelling and Benchmarking

• Martin Schindewolf, David Kramer, Marcelo Cintra:
  Compiler-Directed Performance Model Construction for Parallel Programs. 187-198
  
• Roman Plyaskin, Andreas Herkersdorf:
  A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces. 199-210
  
• Muhammad Yasir Qadri, Dorian Matichard, Klaus D. McDonald-Maier:
  JetBench: An Open Source Real-time Multiprocessor Benchmark. 211-221
  

Accelerators and GPUs

• Fabian Nowak, Rainer Buchty:
  A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics. 222-233
  
• Xudong Fang, Yuhua Tang, Guibin Wang, Tao Tang, Ying Zhang:
  Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model. 234-245
  

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