ARC 2011: Belfast, UK

Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek A. El-Ghazawi (Eds.): Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Lecture Notes in Computer Science 6578 Springer 2011, ISBN 978-3-642-19474-0

Plenary Talks

Gordon J. Brebner:
Reconfigurable Computing for High Performance Networking Applications. 1
Steve Furber:
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform. 2

Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev:
A Reconfigurable Audio Beamforming Multi-Core Processor. 3-15
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Regular Expression Matching Circuit Based on a Decomposed Automaton. 16-28
Michael Grand, Lilian Bossuet, Bertrand Le Gal, Guy Gogniat, Dominique Dallet:
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios. 29-40

Samuel Bayliss, George A. Constantinides:
Application Specific Memory Access, Reuse and Reordering for SDRAM. 41-52
Christophe Alias, Bogdan Pasca, Alexandru Plesco:
Automatic Generation of FPGA-Specific Pipelined Accelerators. 53-66
Alexandre Cornu, Steven Derrien, Dominique Lavenier:
HLS Tools for FPGA: Faster Development with Better Performance. 67-78

Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate-askasua, Imanol Martinez:
A (Fault-Tolerant)² Scheduler for Real-Time HW Tasks. 79-87
Subhasis Das, Sachin Patkar:
A Compact Gaussian Random Number Generator for Small Word Lengths. 88-93
Manouk V. Manoukian, George A. Constantinides:
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations. 94-101
Janardhan Singaraju, John A. Chandy:
Active Storage Networks for Accelerating K-Means Data Clustering. 102-109
Mario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda:
An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems. 110-117
Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
CReAMS: An Embedded Multiprocessor Platform. 118-124
Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. 125-132

Xuezheng Chu, John McAllister, Roger Woods:
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. 133-144
Stefan Schulze, Sergei Sawitzki:
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL. 145-156
Jair Fajardo Junior, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
Towards an Adaptable Multiple-ISA Reconfigurable Processor. 157-168

Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments. 169-180
Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk:
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. 181-192
Jon T. Butler, Tsutomu Sasao:
Index to Constant Weight Codeword Converter. 193-205
Mauricio Vanegas, Leonardo Rubio, Matteo Tomasi, Javier Díaz, Eduardo Ros:
On-Chip Ego-Motion Estimation Based on Optical Flow. 206-217

Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. 218-229
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami:
Dynamic V_DD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. 230-241
Hironobu Morita, Minoru Watanabe:
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. 242-252

François Duhem, Fabrice Muller, Philippe Lorenzini:
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. 253-260
Andreas Engel, Björn Liebig, Andreas Koch:
Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. 261-268
Francisco Barranco, Matteo Tomasi, Javier Díaz, Eduardo Ros:
Hierarchical Optical Flow Estimation Architecture Using Color Cues. 269-274
Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert:
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. 275-280
Kevin Cunningham, Prawat Nagvajara:
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers. 281-286
Christophe Le Lann, David Boland, George A. Constantinides:
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. 287-295
Traian Tulbure:
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology. 296-301

Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang:
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. 302-315
Nikolaos Alachiotis, Alexandros Stamatakis:
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit. 316-327
Sascha Mühlbach, Andreas Koch:
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security. 328-339

Weibo Pan, William P. Marnane:
A Correlation Power Analysis Attack against Tate Pairing on FPGA. 340-349
Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero:
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. 350-362

Pavel G. Zaykov, Georgi Kuzmanov:
Architectural Support for Multithreading on Reconfigurable Hardware. 363-374
Séamas McGettrick, Kunjan Patel, Chris J. Bleakley:
High Performance Programmable FPGA Overlay for Digital Signal Processing. 375-384
Alexander Biedermann, Marc Stöttinger, Lijing Chen, Sorin A. Huss:
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture. 385-396

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