ARC 2009: Karlsruhe, Germany

Keynotes

• Brent E. Nelson:
  FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda. 1
  
• Joseph Hassoun:
  Resiliency in Elemental Computing. 2
  
• Ian Phillips:
  The Colour of Embedded Computation. 3
  

Applications 1

• Heiner Litz, Holger Fröning, Ulrich Brüning:
  A HyperTransport 3 Physical Layer Interface for FPGAs. 4-14
  
• Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
  Parametric Design for Reconfigurable Software-Defined Radio. 15-26
  

Applications 2

• Juan Carlos Moctezuma Eugenio, Miguel Arias-Estrada:
  Hardware/Software FPGA Architecture for Robotics Applications. 27-38
  
• Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David:
  Reconfigurable Operator Based Multimedia Embedded Processor. 39-49
  

FPGA Security and Bitstream Analysis

• Saar Drimer, Markus G. Kuhn:
  A Protocol for Secure Remote Updates of FPGA Configurations. 50-61
  
• Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
  FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. 62-73
  

Fault Tolerant Systems

• Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
  An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. 74-84
  
• Luca Sterpone:
  Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. 85-96
  

Architectures

• Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
  A Novel Local Interconnect Architecture for Variable Grain Logic Cell. 97-109
  
• Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro:
  Dynamically Adapted Low Power ASIPs. 110-122
  
• Mao Nakajima, Minoru Watanabe:
  Fast Optical Reconfiguration of a Nine-Context DORGA. 123-132
  

Place and Route Techniques

• Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung:
  Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. 133-144
  
• Ricardo S. Ferreira, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso:
  On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks. 145-156
  
• Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini:
  A New Datapath Merging Method for Reconfigurable System. 157-168
  

Cryptography

• Xu Guo, Patrick Schaumont:
  Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform. 169-180
  
• Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro:
  Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. 181-192
  
• Gang Zhou, Harald Michalik, László Hinsenkamp:
  Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. 193-203
  

Resource Allocation and Scheduling

• Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan:
  Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. 204-215
  
• Yi Lu, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev:
  Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. 216-230
  

Applications 3

• Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
  Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. 231-242
  
• Kofi Appiah, Andrew Hunter, Tino Kluge, Philip Aiken, Patrick Dickinson:
  FPGA-Based Anomalous Trajectory Detection Using SOFM. 243-254
  

Posters

• José Manuel Moya, Javier Rodríguez, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio:
  SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems. 255-260
  
• Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
  A Parallel Branching Program Machine for Emulation of Sequential Circuits. 261-267
  
• Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
  Memory Sharing Approach for TMR Softcore Processor. 268-274
  
• Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin:
  The Need for Reconfigurable Routers in Networks-on-Chip. 275-280
  
• Fernando Rincón, Jesús Barba, Francisco Moya, Juan Carlos López, Julio Dondo:
  Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware. 281-286
  
• Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan:
  Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. 287-292
  
• Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Morisothi Yasunaga:
  Tile-Based Fault Tolerant Approach Using Partial Reconfiguration. 293-299
  
• SangKyun Yun, KyuHee Lee:
  Regular Expression Pattern Matching Supporting Constrained Repetitions. 300-305
  
• Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr:
  Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function. 306-311
  
• Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga:
  AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. 312-317
  
• Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos:
  CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers. 318-323
  
• Sirisak Leephokhanon, Theerayod Wiangtong:
  Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System. 324-329
  
• Raphael Weber, Achim Rettberg:
  Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. 330-335
  
• Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire:
  A Hardware Accelerated Simulation Environment for Spiking Neural Networks. 336-341
  
• Yahya Jan, Lech Józwiak:
  Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. 342-348
  
• Beniamin Apopei, Andy Mills, Tony J. Dodd, Haydn Thompson:
  Real Time Simulation in Floating Point Precision Using FPGA Computing. 349-354
  
• Brian Baldwin, Richard Moloney, Andrew Byrne, Gary McGuire, William P. Marnane:
  A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem. 355-361
  
• Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl:
  A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems. 362-367
  
• Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri:
  Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. 368-373
  
• Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick:
  ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach. 374-379
  
• Markus Happe, Enno Lübbers, Marco Platzner:
  A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. 380-385
  

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