9. ACSD 2009: Augsburg, Germany

Invited Papers

• Stephen B. Furber, Andrew D. Brown:
  Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors. 3-12
  
• Gerhard Schellhorn, Simon Bäumler:
  Formal Verification of Lock-Free Algorithms. 13-18
  
• Yosinori Watanabe:
  Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. 19
  

Regular Papers

• Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards:
  Teak: A Token-Flow Implementation for the Balsa Language. 23-31
  
• Jens Brandt, Mike Gemunde, Klaus Schneider:
  Desynchronizing Synchronous Programs by Modes. 32-41
  
• Dumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin:
  From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations. 42-51
  
• Josep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky:
  Scheduling Synchronous Elastic Designs. 52-59
  
• Silvia Crafa, Francesco Ranzato, Francesco Tapparo:
  Saving Space in a Time Efficient Simulation Algorithm. 60-69
  
• Victor Khomenko, Roland Meyer:
  Checking pi-Calculus Structural Congruence is Graph Isomorphism Complete. 70-79
  
• Niels Lohmann, Karsten Wolf:
  Petrifying Operating Guidelines for Services. 80-88
  
• Sebastian Mauser, Robert Lorenz:
  Variants of the Language Based Synthesis Problem for Petri Nets. 89-98
  
• Andrey Mokhov, Victor Khomenko, Alexandre Yakovlev:
  Flat Arbiters. 99-108
  
• Arjan J. Mooij, Marc Voorhoeve:
  Trading Off Concurrency to Generate Behavioral Adapters. 109-118
  
• Jean-Baptiste Raclet, Eric Badouel, Albert Benveniste, Benoît Caillaud, Roberto Passerone:
  Why Are Modalities Good for Interface Theories?. 119-127
  
• Matthias Raffelsieper, Jan-Willem Roorda, Mohammad Reza Mousavi:
  Model Checking Verilog Descriptions of Cell Libraries. 128-137
  
• Hind Rakkay, Hanifa Boucheneb, Olivier H. Roux:
  Time Arc Petri Nets and Their Analysis. 138-147
  
• Partha S. Roop, Alain Girault, Roopak Sinha, Gregor Goessler:
  Specification Enforcing Refinement for Convertibility Verification. 148-157
  
• Antti Siirtola, Juha Kortelainen:
  Parameterised Process Algebraic Verification by Precongruence Reduction. 158-167
  
• Karsten Wolf, Christian Stahl, Janine Ott, Robert Danitz:
  Verifying Deadlock- and Livelock Freedom in an SOA Scenario. 168-177
  
• Josep Carmona, Jordi Cortadella, Michael Kishinevsky:
  Genet: A Tool for the Synthesis and Mining of Petri Nets. 181-185
  
• Mark Schäfer, Dominic Wist, Ralf Wollowski:
  DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers. 186-190
  

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