2. ACSD 2001: Newcastle upon Tyne, UK

2nd International Conference on Application of Concurrency to System Design (ACSD 2001), 25-30 June 2001, Newcastle upon Tyne, UK. IEEE Computer Society 2001, ISBN 0-7695-1071-X

Invited Talks

Gerard J. Holzmann:
From Code to Models. 3-10
Jeff Kramer:
Making Meaningful Models for Mere Mortal. 11-12
Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. 13-

Performance Issues

Thomas Arts, Izak van Langevelde:
Correct Performance of Transaction Capabilities. 35-42
Wlodzimierz M. Zuberek:
Analysis of Performance Limitations in Multithreaded Multiprocessor Architectures. 43-52
Jan Jürjens:
Abstracting from Failure Probabilities. 53-

Asynchronous Communication

Fei Xia, Ian G. Clark:
Algorithms for Signal and Message Asynchronous Communication Mechanisms and Their Analysis. 65-

Refinement Issues

Sibylle Peuker:
Property Preserving Transition Refinement with Concurrent Runs: An Example. 77-86
Jonathan Burton, Maciej Koutny, Giuseppe Pappalardo:
Implementing Communicating Processes in the Event of Interface Difference. 87-

Object-Oriented Approach

Stanislav Chachkov, Didier Buchs:
From Formal Specifications to Ready-to-Use Software Components: The Concurrent Object Oriented Petri Net Approach. 99-

Codesign and Embedded Systems

Ricardo Jorge Machado, João M. Fernandes:
A Petri Net Meta-Model to Develop Software Components for Embedded Systems. 113-122
Martin Grajcar:
Strength and Weaknesses of Genetic List Scheduling for Heterogeneous Systems. 123-132
Charles Andre, Frédéric Boulanger, Alain Girault:
Software Implementation of Synchronous Programs. 133-142
Klaus Schneider:
Embedding Imperative Synchronous Languages in Interactive Theorem Provers. 143-

Asynchronous Circuits

Josep Carmona, Jordi Cortadella, Enric Pastor:
A structural encoding technique for the synthesis of asynchronous circuits. 157-166
Oscar Garnica, Juan Lanchares, Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. 167-178
Nikolai Starodoubtsev, Sergei Bystrov, Michael V. Goncharov, Ilya V. Klotchkov, Alexander B. Smirnov:
Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs. 179-188
Radu Negulescu, Xiaohua Kong:
Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits. 189-

Verification and Testing

Juhana Helovuo, Sari Leppänen:
Exploration Testing. 201-210
Louise Lorentsen, Lars Michael Kristensen:
Exploiting Stabilizers and Parallelism in State Space Generation with the Symmetry Method. 211-220
Miguel J. Hornos, Manuel I. Capel:
Automata Generation for On-the-fly Automatic Verification Using Formulas of an Interval Logic. 221-230
Michael Baldamus, Klaus Schneider:
The BDD Space Complexity of Different Forms of Concurrency. 231-

Petri Net Synthesis

Marta Pietkiewicz-Koutny:
Synthesis of Net Systems with Inhibitor Arcs from Step Transition Systems. 245-254

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