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5.
ACAC
2000: Canberra, ACT, Australia
5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia. IEEE Computer Society 2000, ISBN 0-7695-0512-0
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dblp key:
conf/aPcsac/CheungAE00
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Hon Nin Cheung
,
Li-Minn Ang
,
Kamran Eshraghian
:
Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm.
3-8
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conf/aPcsac/ChuL00
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Wanming Chu
,
Yamin Li
:
Cost/Performance Tradeoff of n-Select Square Root Implementations.
9-16
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conf/aPcsac/EeckhoutBN00
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Lieven Eeckhout
,
Koen De Bosschere
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Henk Neefs
:
On the Feasibility of Fixed-Length Block Structured Architectures.
17-25
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conf/aPcsac/Gunther00
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Bernard K. Gunther
:
The Circuit Object Organization Library.
26-33
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conf/aPcsac/JesshopeL00
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Chris R. Jesshope
,
Bing Luo
:
Micro-Threading: A New Approach to Future RISC.
34-41
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conf/aPcsac/LeeM00
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Gareth Lee
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John Morris
:
Dataflow Java: Implicitly Parallel Java.
42-50
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conf/aPcsac/LundTC00
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T. Lund
,
Antonio Jesús Torralba Silgado
,
Ramón González Carvajal
:
The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip.
51-56
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conf/aPcsac/McClureAI00
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Bruce McClure
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T. A. Au
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Jadwiga Indulska
:
Adaptive Middleware for Heterogeneous Defense Networks-An Exploratory Simulation Study.
57-63
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John Morris
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Gary A. Bundell
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Sonny Tham
:
A Scalable Re-Configurable Processor.
64-73
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conf/aPcsac/RoopSR00
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Partha S. Roop
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Arcot Sowmya
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S. Ramesh
:
Automated Component Adaptation by Forced Simulation.
74-81
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conf/aPcsac/SiemersS00
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Christian Siemers
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Sybille Siemers
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Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications.
82-89
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conf/aPcsac/TateSS00
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Daniel Tate
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Gordon Steven
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Fleur L. Steven
:
Static Scheduling for Out-of-order Instruction Issue Processors.
90-96
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conf/aPcsac/WigginsH00
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Adam Wiggins
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Gernot Heiser
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Fast Address-Space Switching on the StrongARM SA-1100 Processor.
97-