PACT 2009: Raleigh, North Carolina, USA

Software Transactional Memory and Speculation

• Takayuki Usui, Reimer Behrends, Jacob Evans, Yannis Smaragdakis:
  Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency. 3-14
  
• Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
  Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. 15-25
  

Best Papers

• Abhishek Bhattacharjee, Margaret Martonosi:
  Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. 29-40
  
• Rajkishore Barik, Vivek Sarkar:
  Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs. 41-52
  
• Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood:
  Quantifying the Potential of Program Analysis Peripherals. 53-63
  

Accelerators

• Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble:
  Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor. 67-76
  
• John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
  A Task-Centric Memory Model for Scalable Accelerator Architectures. 77-87
  

Power and Energy

• Xiaorui Wang, Ming Chen, Charles Lefurgy, Tom W. Keller:
  SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers. 91-100
  
• Wangyuan Zhang, Tao Li:
  Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures. 101-112
  
• Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg:
  Core-Selectability in Chip Multiprocessors. 113-122
  

Tools and Testing

• Tipp Moseley, Dirk Grunwald, Ramesh Peri:
  Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison. 125-135
  
• Maurice Herlihy, Yossi Lev:
  tm_db: A Generic Debugging Library for Transactional Programs. 136-145
  
• Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hill, David A. Wood:
  StealthTest: Low Overhead Online Software Testing Using Transactional Memory. 146-155
  

Innovative Hardware

• Andrew D. Hilton, Neeraj Eswaran, Amir Roth:
  CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. 159-168
  
• Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar Iyer:
  Architecture Support for Improving Bulk Memory Copying and Initialization Performance. 169-180
  
• Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel A. Kinsy, Tina Wen, Srinivas Devadas:
  Oblivious Routing in On-Chip Bandwidth-Adaptive Networks. 181-190
  

Scheduling and Adaptation

• Xiaotong Zhuang, Alexandre E. Eichenberger, Yangchun Luo, Kevin O'Brien, Kathryn M. O'Brien:
  Exploiting Parallelism with Dependence-Aware Scheduling. 193-202
  
• Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
  ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. 203-213
  
• Amir Hormati, Yoonseo Choi, Manjunath Kudlur, Rodric M. Rabbah, Trevor N. Mudge, Scott A. Mahlke:
  Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures. 214-223
  

Novel Cache Systems

• Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang:
  DDCache: Decoupled and Delegable Cache Data and Metadata. 227-236
  
• Md. Mafijul Islam, Per Stenström:
  Zero-Value Caches: Cancelling Loads that Return Zero. 237-245
  
• Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan:
  Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning. 246-257
  

Modeling and Evaluation

• Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller:
  Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. 261-270
  
• Basilio B. Fraguela, Yevgen Voronenko, Markus Püschel:
  Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling. 271-280
  
• Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval:
  Analytical Modeling of Pipeline Parallelism. 281-290
  

Hardware Transactional Memory

• Marc Lupon, Grigorios Magklis, Antonio González:
  FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. 293-302
  
• Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata:
  Improving Signatures by Locality Exploitation for Transactional Memory. 303-312
  
• Leo Porter, Bumyong Choi, Dean M. Tullsen:
  Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading. 313-324
  

Compiler Optimizations

• Konrad Trifunovic, Dorit Nuzman, Albert Cohen, Ayal Zaks, Ira Rosen:
  Polyhedral-Model Guided Loop-Nest Auto-Vectorization. 327-337
  
• Sandya S. Mannarswamy, Ramaswamy Govindarajan, Rishi Surendran:
  Region Based Structure Layout Optimization by Selective Data Copying. 338-347
  
• Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-fook Ngai:
  Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. 348-357
  

Cache Management

• Lei Jin, Sangyeun Cho:
  SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. 361-371
  
• Wanli Liu, Donald Yeung:
  Using Aggressor Thread Information to Improve Shared Cache Management for CMPs. 372-383
  
• Xing Zhou, Wenguang Chen, Weimin Zheng:
  Cache Sharing Management for Performance Fairness in Chip Multiprocessors. 384-393
  

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