6. IEEE INTERACT 2002: Cambridge, Massachusetts, USA

6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA. IEEE Computer Society 2002, ISBN 0-7695-1534-7

Instruction Scheduling

Alexander G. Dean:
Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration. 3-14
Sunghyun Jee, Kannappan Palaniappan:
Dynamically Scheduling VLIW Instructions with Dependency Information. 15-23

Simulation and Profiling

Youfeng Wu:
Accuracy of Profile Maintenance in Optimizing Compilers. 27-38
Ronan Amicel, François Bodin:
Mastering Startup Costs in Assembler-Based Compiled Instruction-Set Simulation. 39-44
Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yuan Chen:
On the Predictability of Program Behavior Using Different Input Data Sets. 45-53

Data Access

R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen:
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. 57-67
Jeonghun Cho, Jinhwan Kim, Yunheung Paek:
A Study on Data Allocation of On-Chip Dual Memory Banks. 68-

Code Size

Huiyang Zhou, Thomas M. Conte:
Code Size Efficiency in Global Scheduling for ILP Processors. 79-90
Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Code Compression by Register Operand Dependency. 91-101
Kim M. Hazelwood, Michael D. Smith:
Code Cache Management Schemes for Dynamic Optimizers. 102-110

Last update Tue Feb 14 04:03:16 2012 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page