MSP 2006: San Jose, California, USA

New twists on memory management

• Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen C. Hunt, James R. Larus:
  Deconstructing process isolation. 1-10
  
• Mojtaba Mehrara, Todd M. Austin:
  Reliability-aware data placement for partial memory protection in embedded processors. 11-18
  
• Melissa E. O'Neill, F. Warren Burton:
  Smarter garbage collection with simplifiers. 19-30
  

Workload optimization

• Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim:
  Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures. 31-40
  
• Michael D. Adams, David S. Wise:
  Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms. 41-50
  
• Shoaib Kamil, Kaushik Datta, Samuel Williams, Leonid Oliker, John Shalf, Katherine A. Yelick:
  Implicit and explicit optimizations for stencil computations. 51-60
  

Keynote talk

• David A. Wood:
  Keynote talk challenges in chip multiprocessor memory systems. 61
  

Transactional memory

• Dan Grossman, Jeremy Manson, William Pugh:
  What do high-level memory models mean for transactions? 62-69
  
• Kunal Agrawal, Charles E. Leiserson, Jim Sukha:
  Memory models for open-nested transactions. 70-81
  
• Benjamin Hindman, Dan Grossman:
  Atomicity via source-to-source translation. 82-91
  

Cache and TLB design

• Lei Jin, Hyunjin Lee, Sangyeun Cho:
  A flexible data to L2 cache mapping approach for future multicore processors. 92-101
  
• Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan Rakvic:
  A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems. 102-111
  

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